DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 134

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7 ATM Cell / HDLC Packet Processing
10.7.1 General Description
The ATM cell / packet processing de-maps the ATM cells or HDLC packets from the receive data stream and maps
ATM cells or HDLC packets into the transmit data stream. ATM cell / packet processing supports any framed or
unframed bit synchronous or byte synchronous (octet-aligned) data stream with a bit or byte rate of 52 MHz or less.
The receive direction extracts the payload from physical data stream, performs cell/packet processing on the
individual lines, and stores the cell/packet data from each line in the FIFO.
The transmit direction removes the cell/packet data for each line from the FIFO, performs cell/packet processing for
each individual line and inserts the payload into the physical data stream.
See
Figure 10-23. ATM Cell / HDLC Packet Functional Diagram
10.7.2 Features
General
•
•
•
ATM Cell Processor
•
•
Up to 4 data lines (ports) each with a bit or byte rate of 0–52 MHz
Supports bit or byte wide, framed or unframed data lines – Each port is programmable as bit synchronous
or octet-aligned, the data stream can be framed or unframed, and the clock can be continuous or gapped.
Bit reordering – The received/transmitted order of the bits as transferred across the system interface is
programmable on a per port basis. i.e., In bit synchronous mode, the first bit received/transmitted by ATM cell /
packet processing can be transferred in bit position 7 (31, 23, 15, or 7) or bit position 0 (24, 16, 8, or 0). In
octet-aligned mode, the bit received/transmitted by ATM cell / packet processing in bit position 7 can be
transferred in bit position 7 (31, 23, 15, or 7) or bit position 0 (24, 16, 8, or 0).
Programmable HEC insertion and extraction – The transmit side can be programmed to accept cells from
the system interface that do or do not contain a HEC byte. If cells are transferred without a HEC byte, the HEC
byte will be computed and inserted. If cells are transferred with a HEC byte, then the transferred HEC byte can
be programmed to be passed through or overwritten with a newly calculated HEC. The receive side can be
programmed to send cells to the system interface that do or don't contain the HEC byte.
Programmable erred cell insertion – An HEC error mask can be programmed for insertion of single or
multiple errors individually or continuously at a programmable rate.
Adapter
Figure 10-23
Clock
Rate
for the location of the Cell/Packet processing block in the DS316x devices.
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
JTAG Test
Access Port
FEAC
DS3 / E3
Transmit
Framer
DS3 / E3
Receive
Formatter
Buffer
Trace
Trail
HDLC
GEN
UA1
FRAC/
PLCP
TX
RX FRAC/
PLCP
Processor
Processor
Processor
RX BERT
Processor
Tx Packet
TX BERT
Packet
Tx Cell
Microprocessor
Cell
Rx
Rx
Interface
FIFO
Tx
FIFO
Rx