DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 44

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3163
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3163N
Manufacturer:
Maxim Integrated
Quantity:
10 000
8.2 Detailed Pin Descriptions
Table 8-2. Detailed Pin Descriptions
n = 1,2,3,4 (port number); Ipu (input with pullup); Oz (output tri-stateable, needs an external pullup or pulldown resistor to keep from floating);
Oa (analog output); Ia (analog input); I/O (bidirectional inout); all unused input pins without pullup should be tied low.
TPOSn /
TLCLKn
TDATn
PIN
TYPE
O
O
Transmit Line Clock Output
TLCLKn: This clock is typically used as the clock reference for the TPOSn / TDATn
and TNEG / TOHMOn signals, but can also be used as the reference for the TOHMIn
/ TSOFIn, TFOHn / TSERn, TFOHENIn and TSOFOn / TDENn / TFOHENOn signals.
This output signal can be inverted.
o
o
o
Transmit Positive AMI / Data Output
TPOSn: When the port line interface is configured for B3ZS, HDB3 or AMI mode and
the framer is not configured for one of the “-OHM” modes (see
on this pin indicates that a positive pulse should be transmitted on the line. The signal
is updated on the positive clock edge of the referenced clock pin if the clock pin signal
is not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TLCLKn line clock output pins, but it can be referenced to
the TCLKOn, TCLKIn, RLCLKn or RCLKOn pins.
This output signal can be inverted.
TDATn: When the port line interface is configured for UNI mode or the framer is
configured for one of the “-OHM” modes (see
signal is output on this pin. The signal is updated on the positive clock edge of the
referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on
the falling edge of the clock. The signal is typically referenced to the TLCLK line clock
output pins, but it can be referenced to the TCLKOn, TCLKIn, RLCLKn or RCLKOn
pins
This output signal can be inverted.
o
o
o
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
CC52: 52 MHz +20 ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
LINE I/O
FUNCTION
Table
10-30), the un-encoded transmit
Table
10-30), a high

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