DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 85

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-39
POS device indicates to PHY port 'N' that it is ready to accept a block of packet data by asserting REN. On clock
edge 3, the PHY device selects port 'N' for transfer by asserting RSX and placing its address on RDATA. On clock
edge 4, PHY port 'N' starts packet transfer by de-asserting RSX, asserting RVAL, placing the first byte of the
packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 5, PHY
port 'N' de-asserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on
RDATA. On clock edge 10, PHY port 'N' places the last byte of the packet on RDATA, and asserts REOP to
indicate that this is the last transfer of the packet. On clock edge 11, the PHY device de-asserts RVAL and REOP
ending the packet transfer process from port 'N' and selects PHY port 'L' for transfer by asserting RSX and placing
its address on RDATA. On clock edge 12, PHY port 'L' starts packet transfer by de-asserting RSX, asserting RVAL,
placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the
packet. On clock edge 13, PHY port 'L' de-asserts RSOX as it leaves RVAL asserted and continues to place
additional bytes of the packet on RDATA.
Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing
8.3.6
Figure 8-40
the A[0]/BSWAP signal controls whether or not to byte swap. In 8-bit mode, the A[0]/BSWAP signal is used as the
LSB of the address bus (A[0]). The selection of databus size is determined by the WIDTH input signal. See also
Section 10.1.1.
From PHY
RSOX
RERR
RDAT
RCLK
Transfer
RVAL
REOP
REN
RSX
Microprocessor Interface Functional Timing
and
shows a multi-port receive interface multiple packet transfer from different ports. On clock edge 1, the
1
Figure 8-42
X
2
3
N
show examples of a 16-bit databus and an 8-bit databus, respectively. In 16-bit mode,
4
P1
5
P2
6
P3
7
…
N
8
P62
9
P63
10
P64
11
L
12
P1
13
P2
14
P3
15
P4
16
L
P5
17
P6
18
P7
19
P8
20
P9