DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 25

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6 MAJOR OPERATIONAL MODES
The major operational modes are determined by the FM[5:0] framer mode bitsand a few other control bits. Unused
features are powered down and the data paths are held in reset. The configuration registers of the unused features
can be written to and read from. The function of some IO pins change in different operational modes. The line
interface operational modes are determined by the LM bit.
6.1 DS3/E3 ATM/Packet Mode
DS3/E3 ATM/Packet mode is a normal mode of operation for the DS316x device, which maps/de-maps ATM cells
or packet data into a DS3 or E3 data stream via the selected mapping mode. Major functional blocks for the
DS3/E3 ATM/Packet mode are shown in
is shown in
Table 6-1. DS3/E3 ATM/Packet Mode Configuration Registers
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-1. DS3/E3 ATM/Packet Mode
MODE
TOHMOn/
RLCLKn
RNEGn/
ROHMIn
RPOSn/
TNEGn/
TLCLKn
RLCVn/
TPOSn/
Table
RDATn
TDATn
6-1.
Clock Rate
Adapter
FM[5:0]
0XX000
0XX000
0XX000
0XX000
0XX000
0XX000
Decoder
Encoder
HDB3
B3ZS/
HDB3
B3ZS/
SIM[1:0]
TUA1
GL.CR1
TAIS
Figure
00
01
10
11
10
11
IEEE P1149.1
JTAG Test
Access Port
FEAC
6-1. Mapping configuration is programmable on per port basis and
DS3 / E3
Framer
DS3 / E3
Transmit
Receive
Formatter
Buffer
Trace
Trail
PORT.CR2
HDLC
PMCPE
X
X
1
1
0
0
GEN
UA1
Rx Packet
Processor
Processor
Processor
RX BERT
Processor
Tx Packet
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx
n = port # (1-4)