DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 111

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.5 Performance Monitor Counter Update Details
The performance monitor counters are designed to count at least one second of events before saturating to the
maximum count. There is a status bit associated with some of the performance monitor counters that is set when
the its counter is greater than zero, and a latched status bit that gets set when the counter changes from zero to
one. There is also a latched status bit that gets set on every event that causes the error counter to increment.
There is a read register for each performance monitor counter. The count value of the counter gets loaded into this
register and the counter is cleared when the update-clear operation is performed. If there is an event to be counted
at the exact moment (clock cycle) that the counter is to be cleared then the counter will be set to a value of one so
that that event will be counted.
The Performance Monitor Update signal affects the counter registers of the following blocks: the BERT, the DS3/E3
framer, the Line Encoder/Decoder, the DS3/E3 PLCP framer, the Cell Processor, and the Packet Processor.
The update-clear operation is controlled by the Performance Monitor Update signal (PMU). The update-clear
operation will update the error counter registers with the value of the error counter and also reset each counter.
The PMU signal can be created in hardware or software. The hardware sources can come from the one second
counter or one of the general-purpose I/O pins, which can be programmed to source this signal. The software
sources can come from one of the per-port control register bits or one of the global control register bits. When
using the software update method, the PMU control bit should be set to initiate the process and when the PMS
status bit gets set, the PMU control bit should be cleared making it ready for the next update. When using the
hardware update method, the PMS bit will be set shortly after the hardware signal goes high, and cleared shortly
after the hardware signal goes low. The latched PMS signal can be used to generate an interrupt for reading the
count registers. If the port is not configured for global PMU signals, the PMS signal from that port should be
blocked from affecting the global PMS status.
Figure 10-7. Performance Monitor Update Logic
10.4.6 Transmit Manual Error Insertion
Transmit errors can be inserted in some of the functional blocks. These errors can be inserted using register bits in
the functional blocks, using the global GL.CR1.TMEI bit, using the port PORT.CR1.TMEI bit, or by using the GPIO6
pin configured for TMEI mode.
There is a transmit error insertion register in the functional blocks that allow error insertion. The MEIMS bit controls
whether the error is inserted using the bits in the error insertion register or using error insertion signals external to
that block. When bit MEIMS=0, errors are inserted using other bits in the transmit error insertion register. When bit
MEIMS=1, errors are inserted using a signal generated in the port or global control registers or using the external
GPIO6 pin configured for TMEI operation.
GPIO8(GPMU) PIN
PORT.CR1.PMUM
PORT.CR1.PMU
GL.CR1.GPMU
GL.CR1.GPM
ONE SEC
1X
00
01
0
1
PMU PMS
COUNTER
other port counters
PERF
GTZ
other ports
GL.SR.GPMS
PORT.SR.PMS