DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 109

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The 8 kHz reference logic tree is shown below.
Figure 10-6. 8KREF Logic
10.4.3 One-Second Reference Generation
The one-second reference signal is used as an option to update the performance registers on a precise one
second interval. The generated internal signal should be about 50% duty cycle and it is derived from the Global 8
kHz reference signal by dividing it by 8000. The low to high edge on this signal will set the GL.SRL.ONESL latched
one second detect bit which can generate an interrupt when the GL.SRIE.ONESIE interrupt enable bit is set. The
low to high edge can also be used to generate performance monitor updates when GL.CR1.GPM[1:0]=1X.
10.4.4 General-Purpose I/O Pins
There are eight general-purpose I/O pins that can be used for general I/O, global signals and per port alarm
signals. Each pin is independently configurable to be a general-purpose input, general-purpose output, global
signal or port alarm. Two of the GPIO pins are assigned to each port and can be programmed to output one or two
alarm statuses using one or two GPIO pins. One of the two pins assigned to each port can be programmed as
global input or output signals. When the device is bonded out (or has ports powered down) to have 1, 2 or 3 ports
active, the GPIO pins associated with the disabled ports will still operate as either general-purpose inputs, general-
purpose outputs or global signals. When the ports are disabled and GL.GIOCR.GPIOx[1:0] = 01, the GPIO pin will
be an output driving low. The 8KREFI, TMEI, and PMU signals that can be sourced by the GPIO pin will be driven
low into the core logic when the GPIO pin is not selected for the source of the signal.
Table 10-12
lists the purpose and control thereof of the general-purpose I/O Pins.
RX PLCP 8KREF
FRAME MODE
RX CLOCK
FROM CLAD
G8KRS[1:0]
TX CLOCK
P8KRS[0]
STS-1 CLK
DS3 CLK
E3 CLK
GPIO4
0
1
G8KRS[1:0]
1
2
3
CLOCK DIVIDER
OTHER
8KREF
PORT
CLOCK DIVIDER
P8KRS[1]
0
1
2
3
0
1
0
1
G8KRS[2]
0
1
G8KIS
0
1
P8KREF
GLOBAL 8KREF
TX PLCP 8KREF
PORT 8KREF