DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 322

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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12.13.2 Receive FIFO Register Map
The receive FIFO block has five registers.
Table 12-46. Receive FIFO Register Map
12.13.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Receive FIFO Reset (RFRST) – When 0, the Receive FIFO will resume normal operations, however, data is
discarded until a start of packet/cell is received after RAM power-up is completed. When 1, the Receive FIFO is
emptied, any transfer in progress is halted, the FIFO RAM is powered down, the associated RDXA signal is forced
low, and all incoming data is discarded. If the port was selected when the reset was initiated, the port will be
deselected, and must be reselected (REN) deasserted with address on RADR or RSX asserted with address on
RDATA) before any transfer will occur.
(1,3,5,7)9Ch
(1,3,5,7)9Ah
(1,3,5,7)9Eh
(1,3,5,7)90h
(1,3,5,7)92h
(1,3,5,7)94h
(1,3,5,7)96h
(1,3,5,7)98h
Address
15
--
--
0
7
0
FF.RSRIE
FF.RLCR
FF.RPAC
FF.RSRL
Register
FF.RCR
--
--
--
14
--
--
0
6
0
FIFO Receive Level Control Register
Unused
Unused
FIFO Receive Control Register
FIFO Receive Port Address Control Register
Unused
FIFO Receive Status Register Latched
FIFO Receive Status Register Interrupt Enable
FF.RCR
FIFO Receive Control Register
(1,3,5,7)90h
13
--
--
0
5
0
Register Description
12
--
0
--
0
4
11
--
--
0
3
0
10
--
--
0
2
0
--
--
9
0
1
0
RFRST
--
8
0
0
1

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