DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 233

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 14: RPDATn Invert (RPDTI). This bit inverts the RPDATn pin when set.
Bit 13: RFOHENIn / RPDENIn Invert (RFOHEI). This bit inverts the RFOHENIn / RPDENIn pin when set.
Bit 12: RPOHSOFn / RSOFOn / RDENn / RFOHENOn Invert (RPOHSI). This bit inverts the RPOHSOFn /
RSOFOn / RDENn / RFOHENOn pin when set.
Bit 10: RPOHn / RSERn Invert (RPOHI). This bit inverts the RPOHn / RSERn pin when set.
Bit 9: ROHSOFn Invert (ROHSI). This bit inverts the ROHSOFn pin when set.
Bit 7: ROHn Invert (ROHI). This bit inverts the ROHn pin when set.
Bit 6: ROHCLKn Invert (ROHCKI). This bit inverts the ROHCLKn pin when set.
Bit 4: RNEGn / RLCVn / ROHMIn Invert (RNEGI). This bit inverts the RNEGn / RLCVn / ROHMIn when set.
Bit 3: RPOSn / RDATn Invert (RPOSI). This bit inverts the RPOSn / RDATn pin when set.
Bit 2: RLCLKn Invert (RLCKI). This bit inverts the RLCLKn pin when set.
Bit 1: RCLKOn / RGCLKn / RPOHCLKn Invert (RCKOI). This bit inverts the RCLKOn / RGCLKn / RPOHCLKn
pin when set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 9: Port Status Register Interrupt Status (PSR) This bit is set when any of the latched status register bits, that
are enabled for interrupt, in the PORT.SRL register are set. The interrupt pin will be driven when this bit is set and
the corresponding GL.ISRIE.PISRIE[4:1] is set.
bits, that are enabled for interrupt, in the B3ZS/HDB3 Line Encoder/Decoder block are set. The interrupt pin will be
driven when this bit is set and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 7: Trail Trace Status Register Interrupt Status (TTSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the trail trace block are set. The interrupt pin will be driven when this bit is set
and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 8: Line Code Status Register Interrupt Status (LCSR) This bit is set when any of the latched status register
TTSR
ROHI
15
15
--
--
0
7
0
7
ROHCKI
RPDTI
FSR
14
14
--
0
6
0
6
PORTINV2
Port IO Invert Control Register 2
(0,2,4,6)4Ch
PORT.ISR
Port Interrupt Status Register
(0,2,4,6)50h
RFOHEI
HSR
13
13
--
--
0
5
0
5
RPOHSI
RNEGI
BSR
12
12
0
0
--
4
4
RPOSI
SFSR
11
11
--
--
0
3
0
3
RPOHI
RLCKI
CPSR
10
10
--
0
2
0
2
ROHSI
RCKOI
PPSR
PSR
9
0
1
0
9
1
FMSR
LCSR
--
--
8
0
0
0
8
0