DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 234

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 6: FEAC Status Register Interrupt Status (FSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the FEAC block are set. The interrupt pin will be driven when this bit is set and the
corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 5: HDLC Status Register Interrupt Status (HSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the HDLC block are set. The interrupt pin will be driven when this bit is set and the
corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 4: BERT Status Register Interrupt Status (BSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the BERT block are set. The interrupt pin will be driven when this bit is set and the
corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 3: System FIFO Status Register Interrupt Status (SFSR) This bit is set when any of the latched status
register bits, that are enabled for interrupt, in either the transmit or receive FIFO block are set. The interrupt pin will
be driven when this bit is set and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 2: Cell/Packet Status Register Interrupt Status (CPSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the active transmit or receive cell processor or packet processor block are set.
The interrupt pin will be driven when this bit is set and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 1: PLCP Status Register Interrupt Status (PPSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active PLCP block are set. The interrupt pin will be driven when this bit is set
and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 0: Framer Status Register Interrupt Status (FMSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active DS3 or E3 framer block are set. The interrupt pin will be driven when this
bit is set and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Performance Monitoring Update Status (PMS) This bits indicates the status of all active performance
monitoring register and counter update signals in this port. It is an “AND” of all update status bits and is not set until
all performance registers are updated and the counters reset. In software update modes, the update request bit
PORT.CR1.PMU should be held high until this status bit goes high.
0 = The associated update request signal is low
1 = The requested performance register updates are all completed
15
--
--
7
14
--
--
6
PORT.SR
Port Status Register
(0,2,4,6)52h
13
--
--
5
12
--
--
4
11
--
--
3
Reserved
10
--
2
Reserved
--
9
1
PMS
--
8
0