DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 296

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 1: Parity Error Count Interrupt Enable (PECIE) – This bit enables an interrupt if the PECL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Framing Error Count Interrupt Enable (FECIE) – This bit enables an interrupt if the FECL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 6 to 4: Receive Payload Type (RPT[2:0]) – These three bits are the integrated version of the payload type
(MA[3:5]) from the MA byte.
Bits 3 to 0: Receive Timing Source Indication (TI[3:0]) – When timing source indicator extraction is enabled,
these four bits are the integrated version of the four timing source indicator bits extracted from the last three bits of
the MA byte (MA[6:8]). When timing source indicator bit extraction is disabled, TI[3] is zero, and TI[2:0] contain the
integrated version of the last three bits of the MA byte.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Receive GC Byte (RGC[7:0]) – These eight bits are the integrated version of the GC byte as
extracted from the E3 frame.
Bits 7 to 0: Receive NR Byte (RNR[7:0]) – These eight bits are the integrated version of the NR byte as extracted
from the E3 frame.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
RGC7
RNR7
15
15
--
--
0
7
0
0
7
0
RGC6
RNR6
RPT2
14
14
--
0
6
0
0
6
0
E3G832.RMABR
E3 G.832 Receive MA Byte Register
(1,3,5,7)30h
E3G832.RNGBR
E3 G.832 Receive NR and GC Byte Register
(1,3,5,7)32h
RGC5
RNR5
RPT1
13
13
--
0
5
0
0
5
0
RGC4
RNR4
RPT0
12
12
--
0
0
0
0
4
4
RGC3
RNR3
TI3
11
11
--
0
3
0
0
3
0
RGC2
RNR2
TI2
10
10
--
0
2
0
0
2
0
RGC1
RNR1
TI1
--
9
0
1
0
9
0
1
0
RGC0
RNR0
TI0
--
8
0
0
0
8
0
0
0