DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 81

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-35
PHY ports/devices. Prior to clock edge 1, a packet data transfer was initiated from PHY port '1', and PHY ports '2',
'3', and '4' indicated to the POS device that they have a block of packet data or an end of packet ready for transfer
by asserting their RDXA. On clock edge 2, the POS device indicates to PHY port '1' that it cannot accept any more
data transfers by removing its address from RADR, and indicates to PHY port '2' that it is ready to accept a block of
packet data by placing its address on RADR and leaving REN asserted. On clock edge 3, PHY port '1' stops
transferring packet data, and PHY port '2' starts a packet transfer by leaving RVAL asserted, placing the first byte
of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge
4, PHY port '2' de-asserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet
on RDATA. On clock edge 8, the POS device de-asserts REN to indicate to PHY port '2' that it cannot accept any
more data transfers. On clock edge 9, PHY port '2' ends the packet transfer process by de-asserting RVAL and tri-
stating its RVAL, RDATA, RSOX, REOP, and RERR outputs. And, the POS device indicates to PHY port '3' that it
is ready to accept a block of packet data by placing its address on RADR and reasserting REN. On clock edge 10,
PHY port '3' continues a packet transfer by asserting RVAL and placing the next byte of packet data on RDATA.
On clock edge 14, PHY port '3' places the last byte of the packet on RDATA, and asserts REOP to indicate that this
is the last transfer of the packet. On clock edge 15, PHY port '3' de-asserts RVAL and REOP ending the packet
transfer process, as well as, de-asserting RDXA to indicate that it does not have another block of packet data or an
end of packet ready for transfer. On clock edge 16, the POS device indicates to PHY port '4' that it is ready to
accept a block of packet data by placing its address on RADR and leaving REN asserted. On clock edge 17, PHY
port '4' starts a packet transfer by leaving RVAL asserted, placing the first byte of the packet on RDATA, and
asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 18, PHY port '4' de-asserts
RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA.
Figure 8-35. POS-PHY Level 2 Receive Multiple Packet Transfer from Different PHY
Ports/Devices (Direct Status Mode)
From PHY
RDXA[1]
RDXA[2]
RDXA[3]
RDXA[4]
Transfer
RDATA
RADR
RSOX
REOP
RERR
RCLK
RVAL
REN
shows a multi-device receive interface in byte transfer mode multiple packet transfer from different
'1'
P34
1
'1'
2
P35
3
P1
4
P2
'2'
5
'2'
…
6
P41
7
P42
8
P43
1F
9
10
P19
11
'3'
P20
12
'3'
…
13
P63
14
P64
15
X
16
X
17
'4'
P1
18
P2
19
'4'
P3
20
P4