DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 284
![IC TRPL ATM/PACKET PHY 400-PBGA](/photos/6/87/68748/400-bga_21-0306_sml.jpg)
DS3163
Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3163.pdf
(384 pages)
Specifications of DS3163
Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Framing Error Count (FEC) – When 0, the framing error count is zero. When 1, the framing error count is
one or more.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 8: Receive Unframed All 1’s Change Latched (RUA1L) – This bit is set when the RUA1 bit changes state.
Bit 7: A Bit Change Latched (ACL) – This bit is set when the RAB bit changes state.
Bit 6: N Bit Change Latched (NCL) – This bit is set when the RNB bit changes state.
Bit 5: Change Of Frame Alignment Latched (COFAL) – This bit is set when the data path frame counters are
updated with a new frame alignment that is different from the previous frame alignment.
Bit 4: Loss Of Frame Change Latched (LOFL) – This bit is set when the LOF bit changes state.
Bit 3: Remote Alarm Indication Change Latched (RDIL) – This bit is set when the RDI bit changes state.
Bit 2: Alarm Indication Signal Change Latched (AISL) – This bit is set when the AIS bit changes state.
Bit 1: Out Of Frame Change Latched (OOFL) – This bit is set when the OOF bit changes state.
Bit 0: Loss Of Signal Change Latched (LOSL) – This bit is set when the LOS bit changes state.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 8: Framing Error Latched (FEL) – This bit is set when a framing error is detected.
Bit 0: Framing Error Count Latched (FECL) – This bit is set when the FEC bit transitions from zero to one.
Reserved
ACL
15
15
15
--
--
--
--
7
7
7
Reserved
NCL
14
14
14
--
--
--
--
6
6
6
E3G751.RSR2
E3 G.751 Receive Status Register #2
(1,3,5,7)26h
E3G751.RSRL1
E3 G.751 Receive Status Register Latched #1
(1,3,5,7)28h
E3G751.RSRL2
E3 G.751 Receive Status Register Latched #2
(1,3,5,7)2Ah
Reserved
COFAL
13
13
13
--
--
--
--
5
5
5
Reserved
LOFL
12
12
12
--
--
--
--
4
4
4
Reserved
Reserved
Reserved
Reserved
RDIL
11
11
11
--
3
3
3
Reserved
Reserved
Reserved
Reserved
AISL
10
10
10
--
2
2
2
Reserved
Reserved
Reserved
Reserved
OOFL
--
9
1
9
1
9
1
RUA1L
LOSL
FECL
FEC
FEL
--
8
0
8
0
8
0
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