DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 75

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-29
transfer was started. On clock edge 4, since no other PHY device has a cell ready for transfer, the ATM device
assumes another cell transfer from PHY device 'N' and leaves REN asserted. On clock edge 5, PHY device 'N'
stops transferring cell data and indicates that it does not have another cell ready for transfer by not asserting
RSOX. On clock edge 6, the ATM device deasserts REN to end the cell transfer process. At the same time, PHY
device 'N' indicates to the ATM device that it now has a complete cell ready for transfer by placing the first byte of
cell data on RDAT, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 7, PHY
device 'N' tri-states its RDAT and RSOX outputs because REN is deasserted. On clock edge 8, the ATM device
selects PHY device 'N'. On clock edge 9, the ATM device asserts REN. On clock edge 10, PHY device 'N'
continues the cell transfer by placing the second byte of cell data on RDAT, and deasserting RSOX.
Figure 8-29. UTOPIA Level 2 Receive Unexpected Multiple Cell Transfer
Cell From:
Transfer
RADR
RDAT
RCLK
RPXA
RSOX
REN
shows a multi-device receive interface unexpected multiple cell transfer. Prior to clock edge 1, the cell
L
P45 P46 P47 P48
1
1F
L
2
N
M
3
1F
M
4
N
5
1F
N
X
6
N
H1
O
7
1F
O
8
N
9
1F
N
10 11 12 13 14 15 16 17 18
H2
P
H3
1F
P
H4
L
1F
P1
L
P2
M
N
1F
P3
M
P4
O
1F
P5
O
P6
P
19 20
1F
P7
P
P8
L