DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 77

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3163
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3163N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Figure 8-31
the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it can accept cell
data by asserting TPXA. On clock edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device
starts a cell transfer to PHY port 'N' by asserting TEN, placing the first byte of cell data on TDATA, and asserting
TSOX to indicate the transfer of the first byte of the cell. On clock edge 7, the ATM device de-asserts TSOX as it
continues to place additional bytes of the cell on TDATA. On clock edge 11, the ATM device polls PHY port 'M'. On
clock edge 12, the ATM device polls PHY port 'N'. On clock edge 13, PHY port 'M' indicates that it can accept the
transfer of a complete cell. On clock edge 14, PHY port 'N' indicates that it cannot accept the transfer of a complete
cell. On clock edge 16, the ATM device deselects PHY port 'N' and selects PHY port 'M' by de-asserting TEN and
placing PHY port 'M's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell to PHY port
'M' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of
the first byte of the cell. On clock edge 18, the ATM device de-asserts TSOX as it continues to place additional
bytes of the cell on TDATA.
Figure 8-31. UTOPIA Level 3 Transmit Multiple Cell Transfer Polled Mode
Transfer
TDATA
Cell To:
TADR
TSOX
TCLK
TPXA
TEN
M
K
X
shows a multi-port transmit interface multiple cell transfer to different PHY devices. On clock edge 1,
1
N
L
X
2
O
M
X
3
N
P
X
4
Q
O
X
5
N
P
X
6
H1
Q
R
7
H2
X
J
8
H3
K
R
9
10
N
P43
L
J
11
P44
M
K
12
P45
N
L
13
P46
M
O
14
P47
P
N
15
P48
Q
O
16
M
P
X
17
H1
R
Q
18
M
H2
X
J
19
H3
R
K
20
P1
L
J

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