DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 58

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RMOD[1:0]
D[15:0]
RERR
RVAL
PIN
TYPE
I/O
Oz
Oz
Oz
Receive packet data Valid(tri-state)
This signal is tri-state when global reset is applied.
RVAL: In POS-PHY L2 or POS-PHY L3 modes, this signal is used to indicate the
validity of a receive data transfer. When RVAL is high, the receive data bus (RDATA,
RPRTY, RSOX, REOP, RMOD, and RERR) is valid and a packet data transfer
occurs. When RVAL is low, the receive data bus is invalid and a data transfer does
not occurs. This signal is updated on the rising edge of RSCLK.
RVAL goes high when a port is selected for packet data transfer and the port has a
programmable size block of data or an end of packet ready for transfer. In POS-PHY
L2 mode, RVAL goes low if the selected port is empty, at the end of a packet, or
when REN is de-asserted. Once RVAL goes low, it will remain low until REN is de-
asserted.
In POS-PHY L3 mode, RVAL goes low if the selected port is empty or at the end of a
packet if the minimum de-assertion time is greater than zero. RVAL will remain de-
asserted for the programmable minimum de-assertion time.
In UTOPIA L3 mode, this signal is held low.
In POS-PHY L2 mode, this signal is driven when one of the ports is selected for data
transfer, and tri-stated when REN is deasserted, none of the ports is selected or data
path reset is active.
In UTOPIA L2 (reset default) mode this signal is tri-stated.
In all UTOPIA L3 or POS-PHY L3 modes this signal is driven.
Receive packet data Modulus [1:0] (tri-state)
This signal is tri-state when global reset is applied.
RMOD[1:0]: In POS-PHY L2 or POS-PHY L3 modes, this signal is used to indicate
the number of valid bytes on the RDATA bus.
This signal is updated on the rising edge of RSCLK.
RMOD is only valid when REOP is high.
In UTOPIA L3, 8-bit POS-PHY L2 or 8-bit POS-PHY L3 modes, RMOD[1:0] signals
are held low.
In 16-bit POS-PHY L2 or 16 bit POS-PHY L3 modes, RMOD[1] is held low.
In POS-PHY L2 mode, these signals are driven when one of the ports is selected for
data transfer, and tri-stated when REN is deasserted, none of the ports is selected or
data path reset is active.
In UTOPIA L2 (reset default) mode these signals are tri-stated.
In UTOPIA L3 or POS-PHY L3 modes these signals are driven.
Receive packet Error (tri-state)
This signal is tri-state when global reset is applied.
RERR: In POS-PHY L2 or POS-PHY L3 modes, this signal is used to indicate that
the current packet is erred. When RERR is high, the current packet should be
aborted. This signal is updated on the rising edge of RSCLK.
RERR is only valid when REOP is high.
In UTOPIA L3 mode this signal is held low.
In POS-PHY L2 mode, this signal is driven when one of the ports is selected for data
transfer, and tri-stated when REN is deasserted, none of the ports is selected or data
path reset is active.
In UTOPIA L2 (reset default) mode this signal is tri-stated.
In UTOPIA L3 or POS-PHY L3 modes, this signal is driven.
Bidirectional 16 or 8-bit data bus
This bus is tri-state when RST pin is low or CS pin is high.
D[15:0]: A 16-bit or 8-bit data bus used to input data during register writes, and data
RMOD[1:0]=00
RMOD[1:0]=01
RMOD[1:0]=10
RMOD[1:0]=11
MICROPROCESSOR INTERFACE
RDATA[31:16] valid
RDATA[31:24] valid
RDATA[31:0] valid
RDATA[31:8] valid
FUNCTION