DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 82
DS3163
Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3163.pdf
(384 pages)
Specifications of DS3163
Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 8-36
PHY ports. On clock edge 2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the
POS device that it can accept a block of packet data by asserting TPXA. On clock edge 4, the POS device selects
PHY port 'N'. On clock edge 5, the POS device starts a packet transfer to PHY port 'N' by asserting TEN, placing
the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet.
On clock edge 6, the POS device de-asserts TSOX as it continues to place additional bytes of the packet on
TDATA. And, PHY port 'N' drives its TSPA output high. On clock edge 10, the POS device polls PHY port 'M'. On
clock edge 11, the POS device asserts TEOP to indicate the transfer of the last byte of the packet to PHY port 'N'
and PHY port 'M' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock
edge 12, the POS device de-asserts TEN to end the packet transfer process to PHY port 'N' and selects PHY port
'M'. On clock edge 13, the POS device starts a packet transfer to PHY port 'M' by asserting TEN, placing the first
byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. And, PHY
port 'N' tri-states its TSPA output. On clock edge 14, the POS device de-asserts TSOX as it continues to place
additional bytes of the packet on TDATA. And, PHY port 'M' drives its TSPA output high.
Figure 8-36. POS-PHY Level 2 Transmit Multiple Packet Transfer to Different PHY Ports
(Polled Status Mode)
Transfer
To PHY
TADR
TSOX
TEOP
TERR
TPXA
TSPA
TDAT
TCLK
TEN
shows a multi-device transmit interface in packet transfer mode multiple packet transfer to different
1
1F
M
X
2
N
X
3
1F
N
X
4
N
X
5
1F
P1
N
6
P2
O
7
1F
P3
O
…
…
8
N
9
P62
1F
L
10
P63
M
11
P64
1F
M
12
M
X
13
1F
P1
M
14
P2
N
15
1F
P3
N
16
M
P4
O
17
1F
P5
O
18
P6
P
19
1F
P7
P
20
P8
L
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