DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 6

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11
12
12.1 R
12.2 G
12.3 UTOPIA/POS-PHY S
12.4 P
12.5 BERT......................................................................................................................................................... 236
12.6 B3ZS/HDB3 L
12.7 HDLC......................................................................................................................................................... 250
12.8 FEAC C
12.9 T
12.10 DS3/E3 F
12.11 F
12.12 DS3/E3 PLCP ........................................................................................................................................... 305
12.13 FIFO R
10.15.2 Features ............................................................................................................................................. 190
10.15.3 Configuration and Monitoring............................................................................................................. 190
10.15.4 Receive Pattern Detection ................................................................................................................. 191
10.15.5 Transmit Pattern Generation.............................................................................................................. 193
OVERALL REGISTER MAP
REGISTER MAPS AND DESCRIPTIONS
12.1.1 Global Register Bit Map ..................................................................................................................... 197
12.1.2 HDLC Register Bit Map...................................................................................................................... 200
12.1.3 T3 Register Bit Map ........................................................................................................................... 202
12.1.4 E3 G.751 Register Bit Map ................................................................................................................ 203
12.1.5 E3 G.832 Register Bit Map ................................................................................................................ 204
12.1.6 Clear-Channel Register Bit Map ........................................................................................................ 205
12.1.7 Fractional Register Bit Map................................................................................................................ 205
12.1.8 Transmit Cell Processor Bit Map ....................................................................................................... 208
12.1.9 Transmit Packet Processor Bit Map................................................................................................... 208
12.2.1 Register Bit Descriptions.................................................................................................................... 212
12.3.1 Transmit System Interface ................................................................................................................. 220
12.3.2 Receive System Interface Register Map............................................................................................ 221
12.4.1 Register Bit Descriptions.................................................................................................................... 224
12.5.1 BERT Register Map ........................................................................................................................... 236
12.5.2 BERT Register Bit Descriptions ......................................................................................................... 237
12.6.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 245
12.6.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 246
12.7.1 HDLC Transmit Side Register Map.................................................................................................... 250
12.7.2 HDLC Receive Side Register Map..................................................................................................... 254
12.8.1 FEAC Transmit Side Register Map.................................................................................................... 258
12.8.2 FEAC Receive Side Register Map..................................................................................................... 261
12.9.1 Trail Trace Transmit Side................................................................................................................... 264
12.9.2 Trail Trace Receive Side Register Map ............................................................................................. 266
12.10.1 Transmit DS3 ..................................................................................................................................... 270
12.10.2 Receive DS3 Register Map................................................................................................................ 272
12.10.3 Transmit G.751 E3 ............................................................................................................................. 280
12.10.4 Receive G.751 E3 Register Map ....................................................................................................... 282
12.10.5 Transmit G.832 E3 Register Map ...................................................................................................... 287
12.10.6 Receive G.832 E3 Register Map ....................................................................................................... 290
12.10.7 Transmit Clear Channel ..................................................................................................................... 298
12.10.8 Receive Clear Channel ...................................................................................................................... 299
12.11.1 Fractional Transmit Side Register Map.............................................................................................. 301
12.11.2 Fractional Receive Side Register Map............................................................................................... 303
12.12.1 Transmit Side PLCP........................................................................................................................... 305
12.12.2 Receive Side PLCP Register Map ..................................................................................................... 309
12.13.1 Transmit FIFO Register Map ............................................................................................................. 318
12.13.2 Receive FIFO Register Map .............................................................................................................. 322
RAIL
RACTIONAL
ER
EGISTERS
LOBAL
P
T
ORT
RACE
EGISTERS
R
ONTROLLER
EGISTERS
RAMER
C
B
OMMON
DS3/E3 .................................................................................................................................. 301
............................................................................................................................................... 264
IT
INE
M
APS
........................................................................................................................................ 270
........................................................................................................................................ 318
E
.................................................................................................................................... 211
.................................................................................................................................... 224
NCODER
................................................................................................................................... 258
.................................................................................................................................. 197
YSTEM
/D
I
NTERFACE
ECODER
....................................................................................................... 245
..................................................................................................... 220
194
197