DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 337

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 11: Out Of Sync (OOS) – This read only bit indicates that a DSS Out Of Sync (OOS) state exists. DSS OOS
occurs when the DSS Scrambler Synchronization state machine is in the "Load" or "Verify" state, and DSS
scrambling has been enabled.
Bit 9: Out Of Cell Delineation (OCD) – This read only bit indicates that an Out of Cell Delineation condition (OCD)
exists. When DSS scrambling is disabled, OCD occurs when the HEC Error Monitoring state machine is in the
"OCD" state. When DSS scrambling is enable, OCD occurs when the DSS OCD Detection state machine is in the
"OCD" state.
Bit 8: Loss Of Cell Delineation (LCD) – This read only bit indicate that a Loss of Cell Delineation state exists.
LCD occurs when OCD persists for the period programmed in the LCD threshold control register RLTC.
Bit 2: Receive Errored Header Cell Count (RECC) – This read only bit indicates that the receive errored header
cell count is non-zero.
Bit 1: Receive Header Pattern Cell Count (RHPC) – This read only bit indicates that the receive header pattern
comparison cell count is non-zero.
Bit 0: Receive Corrected Cell Count (RCHC) – This read only bit indicates that the receive corrected header cell
count is non-zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 11: Out Of Sync Change Latched (OOSL) – This bit is set when the OOS bit in the CP.RSR register changes
state.
Bit 10: Change Of Cell Delineation Latched (COCDL) – This bit is set when the data path cell counters are
updated with a new cell delineation that is different from the previous cell delineation
Bit 9: Out Of Cell Delineation Change Latched (OCDCL) –.This bit is set when the OCD bit in the CP.RSR
register changes state. Note: Immediately after a reset, this bit will be set to one.
Bit 8: Loss Of Cell Delineation Change Latched (LCDCL) – This bit is set when the LCD bit in the CP.RSR
register changes state
Bit 7: Receive Errored Header Cell Latched (RECL) – This bit is set when a cell with an errored header is
discarded.
Bit 6: Receive Corrected Header Cell Latched (RCHL) – This bit is set when a cell with a single header error is
corrected.
RECL
15
15
--
--
--
7
7
RCHL
14
14
--
--
--
6
6
CP.RSR
Cell Processor Receive Status Register
(1,3,5,7)CEh
CP.RSRL
Cell Processor Receive Status Register Latched
(1,3,5,7)D0h
RIDL
13
13
--
--
--
5
5
RUDL
12
12
--
--
--
4
4
RIVDL
OOSL
OOS
11
11
--
3
3
COCDL
RECCL
RECC
10
10
--
2
2
OCDCL
RHPCL
RHPC
OCD
9
1
9
1
RCHCL
LCDCL
RCHC
LCD
8
0
8
0