DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 104

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-4. Reset Sources
Table 10-8. Reset and Power-Down Sources
Register bit states - F0: Forced to 0, F1: Forced to 1, 0: Set to 0, 1: Set to 1, X: Don’t care
0
1
1
1
1
1
1
1
1
1
The reset signals in the device are asynchronous so they no not require a clock to put the logic into the reset state.
Clock signals may be needed to make the logic come out of the reset state.
The power-down function disables the appropriate clocks to cause the logic to generate a minimum of power. Note
that the UTOPIA/POS-PHY system interface logic cannot be powered down, the clocks can not be stopped. The
8KREF and ONESEC circuits can be powered down by disabling the 8KREF source. The CLAD can also be
powered down by disabling it.
PIN
NOTE: Assumes
active high signals
Forced: Internally controlled
Set: User controlled
F0
1
0
0
0
0
0
0
0
0
RST pin
F1
F1
1
1
1
0
0
0
0
0
REGISTER BITS
F0
F0
1
0
0
1
0
0
0
0
F1
F1
F1
X
X
F1
1
1
0
0
D
D
F1
F1
F1
1
0
F1
1
0
1
0
SET
CLR
SET
CLR
Q
Q
Q
Q
GL.CR1. RSTDP
GL.CR1. RST
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
INTERNAL SIGNALS
PORT.CR1.
RSTDP
D
D
D
PORT.CR1. PD
SET
CLR
SET
CLR
SET
CLR
1
1
1
0
0
1
0
0
0
0
Q
Q
Q
Q
Q
Q
PORT.CR1.
RST
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
1
0
Port Data Path Reset
Global Reset
Port Reset
Global Data Path Reset
Port Power Down