DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 17

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3.2 Receive DS3/E3 Framer Features
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3.3 Receive PLCP Framer Features
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3.4 Receive Cell Processor Features
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In UTOPIA bus mode, ports are independently configurable for any ATM protocol
In POS-PHY bus mode, ports are independently configurable for any ATM or HDLC protocol
Programmable to support internally or externally controlled sub-rate DS3 or E3 on any ports
Supports gapped 52 MHz clock rates for signals embedded in SONET/SDH
Optional transmit loop timed clock(s) mode usingthe associated port’s receive clock(s)
Optional transmit clock mode using references generated by the internal Clock Rate Adapter (CLAD)
Requires only a single reference clock for all three data rates using internal CLAD
Clock, data and control signals can be inverted for a direct interface to many other devices
Detection of loss of transmit clock and loss of receive clock
Automatic one-second, external or manual update of performance monitoring counters
Each port can be placed into a low-power standby mode when not being used
Framing and line code error insertion available
Frame synchronization for M23 or C-bit Parity DS3,or G.751 E3 or G.832 E3
B3ZS/HDB3/AMI decoding
Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeroes occurrences
(EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-bit parity errors, BIP-8
errors, and far end block errors (FEBE)
Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of
frame alignment (COFA), receipt of B3ZS/HDB3 codewords, DS3 application ID bit,DS3 M23/C-bit format
mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits
HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
FEAC port for DS3 FEAC channel
16-byte Trail Trace Buffer port for G.832 trail access point identifier
DS3 M23 C bits, and stuff bits configurable as payload or overhead, stored in registers for software inspection
Most framing overhead fields presented on the receive overhead port
Support for internal and external subrate DS3/E3 control (Fractional DS3/E3)
PLCP frame synchronization
C1 cycle/stuff counter interpretation
Detection of out of frame (OOF), BIP-8 errors, FEBE and RAI (Yellow Signal)
Frame timing can be presented on the GPIO2 output pin or used as the transmit PLCP reference
All path overhead fields presented on the PLCP receive overhead port
HDLC port for data link messages on F1, M1 or M2 bytes
Trail Trace port for trace messages on F1 byte
HEC-based cell delineation within the DS3/E3 frame, the PLCP frame, an externally defined frame, or the
entire line bandwidth
Cell de-scrambling using the self-synchronizing scrambler (x
Distributed Sample Scrambler (DSS) for clear-channel ATM (cell-based physical layer)
HEC error detection and correction; HEC discard
Filtering of idle, unassigned and/or invalid cells (provisionable)
Header pattern comparison vs. 32-bit header pattern and mask registers; counting of matching or non-
matching cells; discard of matching or non-matching cells
Four-cell Receive FIFO
Controls include enables/disables/settings for: cell processing, coset polynomial addition, error correction,
erred cell extraction, cell de-scrambling, idle/unassigned/invalid cell filtering, header pattern match
counting/discarding, LCD integration time
Status fields include: out of cell delineation (OCD), loss of cell delineation (LCD) and receipt of idle,
unassigned, invalid, erred, corrected or header-pattern-match cells
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Clear-channel HDLC at line rates up to 52 Mbps
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+1) for ATM over DS3/E3