DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 140

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

multiple errors are considered errored cells. If errored cell extraction is enabled, errored cells are discarded, and
the errored cell count is incremented. If errored cell extraction is disabled, errored cells are passed on. If a cell is
received with an incorrect HEC, HEC error monitoring transitions to the “Detection” state. In the “Detection” state,
good cells are passed on. Cells received with one or more errors are considered errored cells. If m cells are
received with a correct HEC or the data path cell boundary is updated, HEC error monitoring will transition to the
“Correction” state. The value of m is programmable (1, 2, 4, or 8). The HEC Error Monitoring state diagram is
shown in
HEC error monitoring will remain in the “Detection” state. If cell processing is disabled, HEC error monitoring will
not be performed.
Figure 10-26. HEC Error Monitoring State Diagram
HEC byte filtering discards the HEC byte. If HEC transfer is disabled in the receive system interface, the HEC byte
is extracted from the cell and discarded. The resulting 52-byte cell is then passed on for storage in the Receive
FIFO. If HEC transfer is enabled, the 53-byte cell is passed on for storage in the Receive FIFO. If cell processing is
disabled, HEC byte filtering will not be performed.
Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream
DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB
is in DT[7] of the outgoing FIFO data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit received.
Once all cell processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit parallel
data stream and passed on to the Receive FIFO. Cells are stored in the Receive FIFO in a cell format, regardless
of whether or not they are transferred across a UTOPIA or POS-PHY interface. The cell format for a 53-byte cell
with a 32-bit bus is shown in
Figure
Figure 10-27. Cell Format for 53-Byte Cell With 32-Bit Data Bus
10-28.
Figure
Bit 31
C orrection
Payload 41
Payload 45
Payload 1
Payload 5
Header 1
HEC
10-26. HEC Error Monitoring starts in the “Correction” state. If header error correction is disabled,
•
•
•
Payload 42
Payload 46
Figure
Payload 2
Payload 6
Header 2
00h
•
•
•
cell boundary update
10-27. The cell format for a 52-byte cell with a 32-bit bus is shown in
m th good cell
corrected cell
errored cell
Payload 43
Payload 47
Payload 3
Payload 7
Header 3
00h
•
•
•
D etection
Payload 44
Payload 48
Payload 4
Payload 8
Header 4
00h
•
•
•
Bit 0
13
14
2
3
1
4
nd
rd
st
th
th
th
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer