DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 353
![IC TRPL ATM/PACKET PHY 400-PBGA](/photos/6/87/68748/400-bga_21-0306_sml.jpg)
DS3163
Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3163.pdf
(384 pages)
Specifications of DS3163
Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 7: Receive FCS Errored Packet Latched (REPL) – This bit is set when a packet with an errored FCS is
detected.
Bit 6: Receive Aborted Packet Latched (RAPL) – This bit is set when a packet with an abort indication is
detected.
Bit 5: Receive Invalid Packet Detected Latched (RIPDL) – This bit is set when a packet with a non-integer
number of bytes is detected.
Bit 4: Receive Small Packet Detected Latched (RSPDL) – This bit is set when a packet smaller than the
minimum packet size is detected.
Bit 3: Receive Large Packet Detected Latched (RLPDL) – This bit is set when a packet larger than the maximum
packet size is detected.
Bit 2: Receive FCS Errored Packet Count Latched (REPCL) – This bit is set when the REPC bit in the RPPSR
register transitions from zero to one.
Bit 1: Receive Aborted Packet Count Latched (RAPCL) – This bit is set when the RAPC bit in the RPPSR
register transitions from zero to one.
Bit 0: Receive Size Violation Packet Count Latched (RSPCL) – This bit is set when the RSPC bit in the RPPSR
register transitions from zero to one.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) – This bit enables an interrupt if the REPL bit in the
PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 6: Receive Aborted Packet Interrupt Enable (RAPIE) – This bit enables an interrupt if the RAPL bit in the
PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
REPIE
REPL
15
15
--
--
7
0
7
0
RAPIE
RAPL
14
14
--
--
6
0
6
0
PP.RSRL
Packet Processor Receive Status Register Latched
(1,3,5,7)D0h
PP.RSRIE
Packet Processor Receive Status Register Interrupt Enable
(1,3,5,7)D2h
RIPDIE
RIPDL
13
13
--
--
5
0
5
0
RSPDIE
RSPDL
12
12
--
--
0
0
4
4
Reserved
Reserved
RLPDIE
RLPDL
11
11
3
0
3
0
Reserved
Reserved
REPCIE
REPCL
10
10
2
0
2
0
Reserved
Reserved
RAPCIE
RAPCL
9
1
9
0
1
0
Reserved
Reserved
RSPCIE
RSPCL
8
0
8
0
0
0
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