DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 117

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5.6 Trail Trace
There is a single Trail Trace controller for use in line maintenance protocols. The E3-G.832 and PLCP framers can
use the trail trace controller and it is shared automatically since the E3-G.832 and PLCP framing can not be
enabled at the same time.
10.5.7 BERT
There is a Bit Error Rate Test (BERT) circuit for each port for use in generating and detecting test signals in the
payload bits. The BERT can generate and detect PRBS patterns up to 2^32-1 bits as well as repeating patterns up
to 32 bits long. The generated BERT signal replaces the cells or packets from the system interface when the BERT
is enabled by setting the PORT.CR1.BENA.
The cells or packets from the system interface will still be processed using the same bit rate as when the BERT
was not enabled. Any transmit cells will be simply discarded when the BERT is enabled, and any cells or packets
on the line interface will be processed and sent to the system bus when the BERT is enabled. The TDENn and
RDENn pins will still be active but the data on the TSERn pin will be discarded when the BERT is enabled.
10.5.8 Fractional Payload Controller
The Fractional Payload Controller allows the user flexibility to control sub-rate datastreams.
Payload Controller performs fractional overhead/payload data multiplexing. Fractional overhead is sourced from
either an internal register or the external interface. The allocation of the DS3/E3 payload is also controlled either
internally (internally controlled mode) or through the external interface (externally controlled mode).
The third option is Flexible Mode, which allows the user to externally multiplex payload and overhead, bypassing
the Fractional Payload Controller.
10.5.9 PLCP/Fractional port pins
The PLCP/Fractional port pins have multiple functions based on the framing mode the device is in as well as other
pin mode select bits.
10.5.9.1 Transmit PLCP/Fractional port pins
The transmit PLCP/Fractional pins are TSOFIn / TOHMIn, TPOHn / TFOHn / TSERn, TPOHENn / TFOHENIn /
TPDENIn, TPOHSOFn / TSOFOn / TDENn / TFOHENOn, TPDENOn, TPDATn, and TPOHCLKn / TCLKOn /
TGCLKn. They have different functions based on the framing mode and other pin mode bits. Unused input pin
functions should drive a logic zero into the device circuits expecting a signal from that pin. The control bits that
configure
PORT.CR3.TCLKS.
Table 10-18
multiplexed pins.
Table 10-18. TSOFIn / TOHMIn Input Pin Functions
0XXX00 (FRM)
0XXX1X (FRM)
0XXX01 (OHM)
1XX0X1 (OHM)
1XX0X0 (UFRM)
1XX1XX (UFRM)
PORT.CR2
FM[5:0]
the
to
Table 10-24
pins’
TSOFIn
TSOFIn
TOHMIn
TOHMIn
Not used
Not used
modes
Pin function
describe the function selected by the FM bits and other pin mode bits for the
are
PORT.CR2.FM[5:0],
PORT.CR3.TPFPE,
PORT.CR3.TSOFOS
The Fractional
and