DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 331

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Transmit Errored Cell Insertion Finished (TECF) – This bit is set when the number of errored cells
indicated by the TCEN[7:0] bits in the TECC register have been transmitted. This bit is cleared when errored cell
insertion is disabled, or a new errored cell insertion process is initiated.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Transmit Errored Cell Insertion Finished Latched (TECFL) – This bit is set when the TECF bit in the
CP.TSR register transitions from zero to one.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Transmit Errored Cell Insertion Finished Interrupt Enable (TECFIE) – This bit enables an interrupt if the
TECFL bit in the CP.TSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
15
15
15
--
--
--
--
--
--
7
7
0
7
0
14
14
14
--
--
--
--
--
--
6
6
0
6
0
CP.TSR
Cell Processor Transmit Status Register
(1,3,5,7)AEh
CP.TSRL
Cell Processor Transmit Status Register Latched
(1,3,5,7)B0h
CP.TSRIE
Cell Processor Transmit Status Register Interrupt Enable
(1,3,5,7)B2h
13
13
13
--
--
--
--
--
--
5
5
0
5
0
12
12
12
--
--
--
--
--
--
0
0
4
4
4
11
11
11
--
--
--
--
--
--
3
3
0
3
0
10
10
10
--
--
--
--
--
--
2
2
0
2
0
--
--
--
--
--
--
9
1
9
1
9
0
1
0
TECFIE
TECFL
TECF
--
--
--
8
0
8
0
8
0
0
0