DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 212

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bits 15 to 12: Device REV ID Bits 15 to 12 (ID15 to ID12). These bits of the device ID register has same
information as the four bits of JTAG REV ID portion of the JTAG ID register. JTAG ID[31:28].
Bits 11 to 0: Device CODE ID Bits 11 to 0 (ID11 to ID0). These bits of the device code ID register has same
information as the lower 12 bits of JTAG CODE ID portion of the JTAG ID register. JTAG ID[23:12].
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Global Write Mode (GWRM) This bit enables the global write mode. When this bit is set, a write to the
register of any port will write to the same register in all the ports. Reading the registers of any port is not supported
and will read back undefined data.
Bit 14: INT pin mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
Bit 13: Direct Status Enable (DIREN) This bit selects between the direct status and polled status modes for
UTOPIA and POS-PHY.
0 = Normal write mode
1 = Global write mode
0 = Pin is high impedance when not active
1 = Pin drives high when not active
0 = Polled status mode
1 = Direct status mode
GWRM
TMEI
ID15
ID7
15
15
7
0
7
0
MEIMS
INTM
ID14
ID6
14
14
6
0
6
0
GL.IDR
Global ID Register
000h
GL.CR1
Global Control Register 1
002h
DIREN
GPM1
ID13
ID5
13
13
5
0
5
0
GPM0
ID12
ID4
12
12
--
0
0
4
4
SIW1
PMU
ID11
ID3
11
11
3
0
3
0
LSBCRE
SIW0
ID10
ID2
10
10
2
0
2
0
RSTDP
SIM1
ID9
ID1
9
1
9
0
1
1
SIM0
RST
ID8
ID0
8
0
8
0
0
0