DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 74

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3163
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3163N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Figure 8-28
2, the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it has a
complete cell ready for transfer by asserting RPXA. On clock edge 4, the ATM device selects PHY device 'N'. On
clock edge 5, the ATM device asserts REN. On clock edge 6, PHY device 'N' starts a cell transfer by placing the
first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock
edge 7, PHY device 'N' de-asserts RSOX as it continues to place additional bytes of the cell on RDATA. On clock
edge 12, the ATM device polls PHY device 'O'. On clock edge 13, PHY device 'O' indicates to the ATM device that
it has a complete cell ready for transfer by asserting RPXA. On clock edge 16, the ATM device deselects PHY
device 'N' and selects PHY device 'O' by de-asserting REN and placing PHY device 'O's address on RADR. On
clock edge 17, the ATM device asserts REN and PHY device 'N' stops transferring cell data and tri-states its
RDATA and RSOX outputs. On clock edge 18, PHY device 'O' starts a cell transfer by placing the first byte of cell
data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 19, PHY
device 'O' de-asserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 8-28. UTOPIA Level 2 Receive Multiple Cell Transfer Polled Mode
Cell From:
RDATA
Transfer
RSOX
RADR
RCLK
RPXA
REN
shows a multi-device receive interface multiple cell transfer from different PHY devices. On clock edge
M
1
1F
M
2
N
3
1F
N
4
N
5
1F
N
6
H1
O
7
H2
1F
O
8
9
P41
1F
L
10
P42
M
11
N
P43 P44 P45 P46 P47 P48
1F
M
12
O
13
1F
O
14
P
15
1F
P
16
O
17
1F
O
18
H1
N
19
O
H2
1F
N
20
H3
P

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