DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 383

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.7 CLAD Jitter Characteristics
18.8 JTAG Interface AC Characteristics
All AC timing characteristics are specified with a 50pF capacitive load on JTDO pin and 25pF capacitive load on all
other digital output pins, V
The generic timing definitions shown
this interface.
Table 18-8. JTAG Interface Timing
(V
Intrinsic Jitter (UI
Intrinsic Jitter (UI
Peak Jitter Transfer
Note 1:
Note 2:
Note 3:
JTCLK
JTCLK
JTMS and
JTDI
JTMS and
JTDI
JTDO
JTDO
JTDO
Any Digital
Output
Any Digital
Output
Any Digital
Output
Any Digital
Output
Any Digital
Output
Any Digital
Output
DD
NAME(S)
SIGNAL
= 3.3V ±5%, T
JTCLK
Change during Update-DR state.
Change during Update-IR state to or from EXTEST mode.
Change during Update-IR state to or from HIZ mode.
PARAMETER
P-P
RMS
SYMBOL
)
j
)
= -40°C to +125°C.)
t7
t9
f1
t2
t3
t5
t6
t8
t7
t7
t8
t9
t8
t9
IH
= 2.4V and V
Clock Frequency (1/t1)
Clock High or Low Period
Rise/Fall Times
Hold Time from JTCLK Rising Edge
Setup Time to JTCLK Rising Edge
Delay from JTCLK Falling Edge
Delay out of Hi-Z from JTCLK Falling
Edge
Delay to Hi-Z from JTCLK Falling Edge
Delay from JTCLK Falling Edge
Delay from JTCLK Rising Edge
Delay out of Hi-Z from JTCLK Falling
Edge
Delay into Hi-Z from JTCLK Falling Edge
Delay out of Hi-Z from JTCLK Rising
Edge
Delay into Hi-Z from JTCLK Rising Edge
Figure
IL
= 0.8V. The voltage threshold for all timing measurements is VDD/2.
18-1,
DESCRIPTION
MIN
Figure 18-2, Figure 18-3, Figure 18-5,
TYP
0.0045
0.025
MAX
1.75
MIN
20
10
10
0
0
0
0
0
0
0
0
0
0
TYP
UNITS
UI
UI
dB
RMS
P-P
and
MAX
10
20
20
20
20
20
20
20
20
20
5
Figure 18-6
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
apply to
NOTES
2,3
2,3
1
2
1
1