DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 323

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 13 to 8: Receive FIFO Almost Empty Level (RFAE[5:0]) – In POS-PHY packet processing mode, these six
bits indicate the maximum number of four byte groups that can be stored in the Receive FIFO for it to be
considered "almost empty". E.g., a value of 30 (1Eh) results in the FIFO being "almost empty" when it contains 120
(78h) bytes or less. In cell processing mode, RFAE[5:2] are ignored, and RFAE[1:0] indicate the maximum number
of cells that can be stored in the Receive FIFO for it to be considered "almost empty".
Bits 5 to 0: Receive FIFO Almost Full Level (RFAF[5:0]) – In POS-PHY packet processing mode, these six bits
indicate the maximum number of four byte groups that can be available in the Receive FIFO for it to be considered
"almost full". E.g., a value of 30 (1Eh) results in the FIFO being "almost full" when it has 120 (78h) bytes or less
available. In cell processing mode, these bits are ignored.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 4 to 0: Receive FIFO System Port Address (RPA[4:0]) – These five bits set the Receive FIFO system
interface port address used to poll the Receive FIFO for fill status, and select it for data transfer. Each port in the
device must have a different port address. In Level 2 mode, if bits RPA[4:0] are set to a value of 1Fh, the port is
disabled.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Receive FIFO Overflow Latched (RFOL) – This bit is cleared when a logic one is written to this bit, and set
when a Receive FIFO overflow condition occurs. An overflow condition results in a loss of data.
15
15
15
--
--
--
--
--
--
0
7
0
0
7
0
7
14
14
14
--
--
--
--
--
0
6
0
0
6
--
0
6
FF.RLCR
FIFO Receive Level Control Register
(1,3,5,7)92h
FF.RFPAC
FIFO Receive Port Address Control Register
(1,3,5,7)94h
FF.RSRL
FIFO Receive Status Register Latched
(1,3,5,7)98h
RFAE5
RFAF5
13
13
13
--
--
--
0
5
0
0
5
--
0
5
RFAE4
RFAF4
RPA4
12
12
12
1
1
--
0
0
--
--
4
4
4
RFAE3
RFAF3
RPA3
11
11
11
--
--
--
0
3
0
0
3
0
3
RFAE2
RFAF2
RPA2
10
10
10
--
--
--
0
2
0
0
2
0
2
RFAE1
RFAF1
RPA1
--
--
--
9
0
1
0
9
0
1
0
9
1
RFAE0
RFAF0
RFOL
RPA0
--
--
8
0
0
0
8
0
0
0
8
0