DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 18

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3.5 Receive Packet Processor Features
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3.6 Receive FIFO Features
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3.7 Receive System Interface Features
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3.8 Transmit System Interface Features
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3.9 Transmit FIFO Features
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3.10 Transmit Cell Processor Features
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Performance monitoring counters for forwarded cells, corrected cells, uncorrectable cells, header pattern
match/no-match cells, and filtered idle/unassigned/invalid cells
Octet alignment option for externally defined frame formats
Packet de-scrambling using the self-synchronizing scrambler (x
Flag detection, packet delineation, and inter-frame fill discard (flags and all-ones)
Packet abort detection and accumulation
Bit or octet de-stuffing
FCS checking (16-bit or 32-bit), error accumulation, and FCS discard
Packet size checking vs. programmable minimum and maximum size registers
Abort declaration for packets with non-integral number of bytes
Controls include enables/disables/settings for: packet processing, de-scrambling, 16/32-bit FCS, filtering of
FCS erred packets, FCS discard, minimum/maximum packet size
Status fields include: receipt of FCS erred packet, aborted packet, size violation packet, non-integer-length
packets
Performance monitoring counters for forwarded packets, forwarded bytes, aborted bytes, FCS erred packets,
aborted packets, size violation packets (min, max, non-integer-length)
Octet alignment with octet de-stuffing option for externally defined frame formats
Storage capacity for four cells or 256 bytes of packet data per port
Programmable port address
Programmable fill level thresholds
Underflow and overflow status indications
UTOPIA L2 / UTOPIA L3 interface in cell mode, POS-PHY L2 / POS-PHY L3 or SPI-3 interface in packet or
mixed traffic modes
8, 16, or 32-bit data bus at clock rates from 10 MHz to 66 MHz (52 MHz in L2 modes)
Polled and direct cell available outputs
Controls include enables/disables/settings for: HEC transfer, signal inversions, parity enable/polarity, cell
available de-assertion time
UTOPIA L2 / UTOPIA L3 interface in cell mode, POS-PHY L2 / POS-PHY L3 or SPI-3 interface in packet or
mixed traffic modes
8, 16, or 32-bit data bus at clock rates from 10 MHz to 66 MHz (52 MHz in L2 modes)
Polled and direct cell available outputs
Controls include enables/disables/settings for: HEC transfer, signal inversions, parity enable/polarity, cell
available de-assertion time
Storage capacity for four cells or 256 bytes of packet data per port
Programmable port address
Programmable fill level thresholds
Underflow and overflow status indications
Programmable fill cell type
HEC calculation and insertion/overwrite, including coset addition
Cell scrambling using the self-synchronizing scrambler (x
Distributed Sample Scrambler (DSS) for clear-channel ATM (cell-based physical layer)
43
+1) for ATM over DS3/E3
43
+1)