DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 107

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-9. CLAD IO Pin Decode
10.4.2 8 kHz Reference Generation
The 8KREF signal is used to control the rate of PLCP frames to precisely 8000 per second. The global 8KREF
signal is also used to generate the one-second reference signal by dividing it by 8000. This signal can be derived
from almost any clock source on the chip as well as the general-purpose I/O pin GPIO4. The port 8KREF signal
can be sourced from either the global 8KREF signal or from the transmit or receive port clock or from the receive
8KREF signal. The minimum input frequency stability of the 8KREF input pin is ±500 ppm.
The global 8KREF signal can come from an external 8000 Hz reference connected to the GPIO4 general-purpose
I/O pin by setting the GL.CR2.G8KIS bit. The global 8KREF signal can be output on the GPIO2 general-purpose
I.O pin when the GL.CR2.G8KOS bit is set.
The global 8KREF signal can be derived from the CLAD PLL or pins or come from any of the port 8KREF signals
by clearing GL.CR2.G8KIS bit and selecting the source using the GL.CR2.G8KRS[2:0] bits.
The port 8KREF signal can be derived from either the receive PLCP 8KREF signal or from the transmit clock input
pin or input clock pin. The PORT.CR3.P8KRS[1:0] bits are used to select which source.
The transmit PLCP 8KREF signal can be selected to be either the global 8KREF signal or the port 8KREF signal
using the PORT.CR3.P8KREF bit.
The 8KREF 8.000 kHz signal is a simple divisor of 51840 kHz (CC52 divided by 6480), 44736 kHz (DS3 divided by
5592) or 33368 kHz (E3 divided by 4296). The correct divisor for the port 8KREF source is selected by the mode
the port is configured for. The CLAD clock chosen for the clock source selects the correct divisor for the global
8KREF. The 8KREF signal is only as accurate as the clock source chosen to generate it.
Table 10-10
CLAD[3:0]
GL.CR2.
00 XX
01 00
01 01
01 10
01 11
10 00
10 01
10 10
10 11
11 00
11 01
11 10
11 11
lists the selectable sources for global 8 kHz reference sources.
DS3 clock input
DS3 clock input
DS3 clock input
DS3 clock input
DS3 clock input
E3 clock input
E3 clock input
E3 clock input
E3 clock input
STS-1 clock input
STS-1 clock input
STS-1 clock input
STS-1 clock input
CLKA PIN
E3 clock input
Low output
E3 clock output
Low output
STS-1 clock output
Low output
DS3 clock output
Low output
STS-1 clock output
Low output
E3 output
Low output
DS3 clock output
CLKB PIN
STS-1 clock input
Low output
Low output
STS-1 clock output
E3 clock output
Low output
Low output
STS-1 clock output
DS3 clock output
Low output
Low output
DS3 clock output
E3 clock output
CLKC PIN