DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 153

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
from the transmit trail trace controller, or the HDLC Overhead Processor interface). The F1 byte source is
programmable (PLCP.TCR.TF1C[1:0]) (trail trace data link, HDLC, or register).
The fourth byte of subframe 4 is overwritten with the B1 byte which is a BIP-8 calculated over all of the path
overhead bytes and cell bytes of the previous frame after all PLCP processing (frame generation, error insertion,
and overhead insertion) has been completed.
The first four bits of the fourth byte of subframe 3 are overwritten with the G1 byte REI bits (G1[1:4]). The Remote
Error Indication (REI) bits can be generated automatically or inserted from the G1 register bits. The REI source is
programmable (auto or register). If the REI bits are generated automatically, they are set to zero when the receive
side B1 byte exactly matches the BIP-8 calculated for the previous receives side frame. Otherwise, the REI is set to
a value of one to eight to indicate the number of parity errors (BIP-8 errors) detected in the receive PLCP frame (B1
byte).
The fifth bits of the fourth byte of subframe 3 is overwritten with the G1 byte RAI bit (G1[5]). The Remote Alarm
Indication (RAI) bit is sourced from a register.
The last three bits of the fourth byte of subframe 3 are overwritten with the G1 byte LSS bits (G1[6:8]). The Link
Status Signal (LSS) bits are sourced from a register. The three register bits are inserted in the sixth, seventh, and
eighth bits of the G1 byte in each frame.
The fourth byte of subframes 2 and 1 are overwritten with the M2 and M1 bytes respectively. Each byte can be
individually sourced from a register, or from the transmit HDLC Overhead Processor. The M2 byte and M1 byte
sources are each programmable (register or HDLC). If both bytes are programmed to be sourced from the transmit
HDLC controller, they are concatenated as a single data link as opposed to two separate data links.
The fourth byte of subframe 0 is overwritten with the C1 byte created during trailer generation.
Once all of the overhead bytes have been overwritten, the data stream is passed on to error insertion.
10.8.7.3 Transmit E3 PLCP Error Insertion
Error insertion inserts various types of errors into the different overhead bytes. The types of errors that can be
inserted are framing errors, BIP-8 parity errors, and Remote Error Indication (REI) errors.
The type of framing error(s) inserted is programmable (frame bit error or framing byte error). A framing bit error is a
single bit error in a frame alignment byte (A1 or A2) or POI byte (P#). A framing byte error is an error in all eight bits
of a frame alignment byte (A1 or A2) or path overhead indicator (POI) byte (P#). Framing error(s) can be inserted
one error at a time, or in two consecutive bytes (A1 & A2 or P# & P#+1). The framing error insertion rate (single A1
or A2, single P#, A1 & A2, or P# & P#+1) is programmable.
The type of BIP-8 error(s) inserted is programmable (errored BIP-8 bit, or errored BIP-8 byte). An errored BIP-8 bit
is inverting a single bit error in the B1 byte. An errored BIP-8 byte is inverting all eight bits in the B1 byte. BIP-8
error(s) can be inserted one error at a time, or continuously. The BIP-8 error insertion rate (single or continuous) is
programmable.
The type of REI error(s) inserted is programmable (single REI error or eight REI errors). A single REI error is
generated by setting the first four bits of the G1 byte to a value of 1h. Eight REI errors are generated by setting the
first four bits of the G1 byte to a value of 8h. REI error(s) can be inserted one error at a time, or continuously. The
REI error insertion rate (single or continuous) is programmable.
Error insertion can be initiated by a register bit (PLCP.TEIR.TSEI) or initiated by the manual error insertion input
(TMEI). Each error type is individually enabled by a register bit. The error insertion initiation type (register or input)
is programmable. Once all error insertion has been performed, the data stream is passed on to overhead insertion.
10.8.7.4 Transmit E3 PLCP Overhead Insertion
Overhead insertion can insert any (or all) of the path overhead bytes into the E3 PLCP frame. The overhead bytes
Z3 – Z1, F1, B1, G1, M1, M2, and C1 can be sourced from the transmit overhead interface (TPOHCLK, TPOH,
TPOHEN, and TPOHSOF). The B1 and C1 bytes are sourced as error masks (modulo 2 addition of the input
B1/C1 byte and the generated B1/C1 byte). The overhead insertion is fully controlled by the transmit overhead
interface. If the transmit PLCP overhead data enable signal (TPOHEN) is driven high, then the bit on the transmit
PLCP overhead signal (TPOH) is inserted into the output data stream. Insertion of bits using the TPOH signal
overwrites internal overhead insertion.