DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 227

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Transmit Line IO Signal Enable (TLEN). This bit is used to enable to transmit line interface output pins
TLCLKn, TPOSn/TDATn and TNEGn.
Bit 11: Receive ATM Cell Delineation Verify 8 Enable (RCDV8). This bit determines the number of good cells
required for the ATM cell delineator state machine to transition from the “Verify” state to the “Update” state. This
setting also determines how many valid cells required to clear the OCD status bit.
Bit 10: Port Interface Mode (LM). The LM bit selects main port interface operational modes.
Table 10-31. Line Mode Select Bits - LM
Bit 7: Receive Cell Delineator Disable (RCDIS). This bit determines if the ATM cell delineator in the ATM cell
processor is active in PLCP modes. This ATM cell delineator in the ATM cell processor is always active in non-
PLCP ATM cell modes.
Bit 6: POS-PHY Mode Cell Processor Enable (PMCPE). This bit determines the associated transmit and receive
port interface processing (cell/packet) to be performed in the POS-PHY mode. It is only active in POS-PHY mode
when PLCP is not enabled. When PLCP is enabled in POS-PHY mode, cell processing is performed.
Bits 5 to 0: Framing mode (FM[5:0]). The FM[5:0] bits select main framing operational modes. Default: DS3 C-
bit.
LINE.TCR.TZSD &
LINE.RCR.RZSD
0 = Disable, force outputs low
1 = Enable normal operation
0 = Six valid ATM cells are required (typical for framed cells)
1 = Eight valid ATM cells are required (typical for unframed cells)
0 = ATM cell delineation is determined in the ATM cell processor
1 = ATM cell delineation is determined in the PLCP framer (Note: RCDIS = 1 is not a recommended
mode.)
0 = Packet processing will be performed
1 = Cell processing will be performed
X
0
1
RCDIS
TLEN
15
0
7
0
(PORT.CR2)
Reserved
PMCPE
14
LM
0
6
0
0
0
1
PORT.CR2
Port Control Register 2
(0,2,4,6)42h
Reserved
B3ZS/HDB3
AMI
UNI
FM5
13
0
5
0
Line Code
Reserved
FM4
12
0
0
4
RCDV8
FM3
11
0
3
0
FM2
LM
10
0
2
0
Reserved
FM1
9
0
1
0
Reserved
FM0
8
0
0
0