DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 213

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bits 11 and 10: System Interface Bus Width (SIW[1:0]) These bits configure the system bus width.
Bits 9 and 8: System Interface Mode (SIM[1:0]) These bits configure the system bus mode.
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used insert an error in all ports and error insertion logic
configured for global error insertion. An error(s) is inserted at the next opportunity when this bit transitions from low
to high. The GL.CR1.MEIMS bit must be clear for this bit to operate.
Bit 6: Transmit Manual Error Insert Select (MEIMS) This bit is used to select the source of the global manual
error insertion signal
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]) These bits select the global performance
monitor register update mode.
Bit 3: Global Performance Monitor Update Register (PMU) This bit is used to update all of the performance
monitor registers configured to use this bit. When this bit is toggled from low to high the performance registers
configured to use this signal will be updated with the latest count value from the counters, and the counters will be
reset. The bit should remain high until the performance register update status bit (GL.SR.PMS) goes high, then it
should be brought back low which clears the PMS status bit.
Bit 2: Latched Status Bit Clear on Read Enable (LSBCRE). This signal determines when latched status register
bits are cleared.
Bit 1: Reset Data Path (RSTDP). When this bit is set, it will force all of the internal data path registers in all ports
to their default state. This bit must be set high for a minimum of 100ns. See the
10.3. Note: The default state is a 1 (after a general reset, this bit will be set to one).
Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this
RST bit), on all of the ports, will be reset to their default state. This bit must be set high for a minimum of 100ns.
See the
00 = 8-bit
01 = 16-bit
1X = 32-bit
00 = UTOPIA L2
01 = UTOPIA L3
10 = POS-PHY L2
11 = POS-PHY L3 or SPI-3
0 = Global error insertion using TMEI bit
1 = Global error insertion using the GPIO6 pin
00 = Global PM update using the PMU bit
01 = Global PM update using the GPIO8 pin
1x = One second PM update using the internal one second counter
0 = Latched status register bits are cleared on a write
1 = Latched status register bits are cleared on a read
0 = Normal operation
1 = Force all data path registers to their default values
0 = Normal operation
1 = Force all internal registers to their default values
Reset and Power-Down
in Section 10.3.
Reset and Power-Down
section