DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 50

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TPOHSOFn /
TFOHENOn
TPDENOn
TDENn /
PIN
TYPE
O
See
TSOFOn: When the port framer is configured for the External Fractional or Flexible
Fractional modes and the port pins are enabled and the TSOFOn pin function is
selected, this signal is used to indicate the start of the DS3/E3 frame on the TPOHn /
TFOHn / TSERn pin. The signal is also active in the non-PLCP non-fractional DS3 or
E3 framing modes when the port pins are enabled and the TSOFOn pin function is
selected. This signal pulses high three clocks before the first overhead bit in a DS3 or
E3 frame that will be input on TSERn or TFOHn. The signal is updated on the positive
clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise
it is updated on the falling edge of the clock. The signal is typically referenced to the
TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,
RCLKOn and RLCLKn clock pins.
This signal can be inverted.
TDENn: When the port framer is configured for the External Fractional or Flexible
Fractional modes and the port pins are enabled and the TDENn pin function is
selected, this signal is used to mark the DS3/E3 frame bits on the TPOHn / TFOHn /
TSERn pin. The signal is also active in the non-PLCP non-fractional DS3 or E3
framing modes when the port pins are enabled and the TDENn pin function is
selected. The signal goes high three clocks before the start of DS3/E3 payload bits
and goes low three clocks before the end of the DS3/E3 payload bits. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TCLKIn transmit clock input pins, but it can be referenced
to the TLCLKn, TCLKOn, RCLKOn and RLCLKn clock pins.
This signal can be inverted.
TPOHSOFn: When the port framer is configured for one of the PLCP framing modes
and the port pins are enabled, this signal is used to mark the start of a DS3 or E3
PLCP overhead sequence on the TPOHn pins. The sequence starts on the same high
to low transition of the TPOHCLKn clock that this signal is high. This signal is updated
at the same time as the TPOHCLKn signal transitions high to low.
This signal can be inverted.
TFOHENOn: When the port framer is configured for one of the internal fractional
modes and the port pins are enabled, this signal is used to indicate the fractional
overhead bit positions of the data on the TOHn pin. The signal goes high one clock
before the start of DS3/E3 fractional overhead bits and goes low one clock before the
end of the DS3/E3 fractional payload bits. The signal is updated on the positive clock
edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is
updated on the falling edge of the clock. The signal is typically referenced to the
TCLKIn transmit clock input pin, but it can be referenced to the TLCLKn, TCLKOn,
RCLKOn or RLCLKn clock pin.
This signal can be inverted.
Transmit Payload Data Enable Output
See
TPDENOn: When the port framer is enabled for the Flexible fractional mode and the
port pins are enabled, this signal marks which bits on the TPDATn pin are valid
payload data bits. It is high during the same clock cycle the TPDATn payload data bit
is valid. The signal is updated on the positive clock edge of the referenced clock pin if
the clock pin signal is not inverted, otherwise it is updated on the falling edge of the
clock. The signal is typically referenced to the TCLKIn transmit clock input pin, but it
can be referenced to the TLCLKn, TCLKOn, RCLKOn or RLCLKn clock pin.
This signal can be inverted.
Table 10-21.
Table 10-24.
FUNCTION