DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 100

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.3.1 Transmit Line Interface Pins Timing Source Selection
(TPOSn/TDATn, TNEGn/TOHMOn)
The transmit line interface signal pin group has the same functional timing clock source as the TLCLKn pin
described in
output pin is always a valid output clock for external logic to use for these signals when PORT.CR3.TLTS=0.
The transmit line timing select bit (TLTS) is used to select input or output clock pin timing. When TLTS=0, output
clock timing is selected. When TLTS=1, input clock timing is selected. If TLTS is set for input clock timing and an
output clock pin is used, or if TLTS is set for output clock timing and an input clock pin is used, then the setup, hold
and delay timings, as specified in
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the CLAD.
Table 10-5. Transmit Line Interface Signal Pin Valid Timing Source Select
10.2.3.2 Transmit Framer and Fractional Pin Timing Source Selection
(TFOHn/TSERn, TFOHENIn/TPDENIn, TOHMIn/TSOFIn, TSOFOn/TDENn/TFOHENOn, TPDATn, TPDENOn)
The transmit framer and fractional signal pin group has the same functional timing clock source as the TCLKO pin
described in
is always a valid output clock for external logic to use for these signals when TFTS=0.
The transmit framer and fractional timing select bit (TFTS) is used to select input or output clock pin timing. When
TFTS=0, output clock timing is selected. When TFTS=1, input clock timing is selected. If TFTS is set for input clock
timing and an output clock pin is used, or If TFTS is set for output clock timing and an input clock pin is used, then
the setup, hold and delay timings, as specified in
TFTS=1 and other modes in which there is no input clock pin available for external timing since the clock source is
derived internally from the CLAD.
1
1
0
0
0
0
0
0
0
not LLB (010) and not PLB (011)
not LLB (010) and not PLB (011)
not LLB (010), not PLB (011)
Table
Table
and not LLB&DLB (110)
and not LLB&DLB (110)
and not LLB&DLB (110)
LLB (010) or PLB (011)
LLB (010) or PLB (011)
or DLB&LLB (110)
DLB&LLB (110)
not DLB (100),
10-3. Other clock pins can be used for the external timing. The TCLKO transmit clock output pin
10-2. Other clock pins can be used for the external timing. The TLCLKn transmit line clock
DLB (100)
LBM[2:0]
XXX
XXX
Table 18-1,
will not be valid. There are some combinations of TLTS=1 and other
X
X
X
X
X
X
X
0
1
Table
0
1
0
0
0
0
1
1
1
18-1, will not be valid. There are some combinations of
Valid Timing to These Clock Pins
TLCLKn, TCLKOn, RCLKOn
RLCLKn
TLCLKn, TCLKOn, RCLKOn
TLCLKn, RCLKOn
TLCLKn
TLCLKn, TCLKOn (default)
No valid timing to any input clock pin
TCLKIn
RLCLKn