DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 166

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are absent.
Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off) via the T3.TCR.PBGE register bit. The P-bits will be
generated if either P-bit generation is enabled or frame generation is enabled.
The bits C
The bit C
The bits C
The bits C
generated automatically or inserted from a register bit. The FEBE bit source is programmable (automatic or
register). If the T3.TCR.AFEBED register bit is one then the T3.TCR.TFEBE register bit controls this bit. If the
FEBE bit is generated automatically, it is zero when at least one C-bit parity error has been detected during the
previous frame.
The bits C
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on to error insertion. Frame generation is programmable
(on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
10.10.5.3 Transmit C-bit DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors, P-bit parity errors, C-bit parity errors, and Far-End Block Error (FEBE) errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single subframe
alignment bit (F
error in all the subframe alignment bits in a subframe (F
alignment bit (M
A P-bit parity error is generated by is inverting the value of the P-bits (P
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
A C-bit parity error is generated by is inverting the value of the C
parity error(s) can be inserted one error at a time, or continuously. The C-bit parity error insertion mode (single or
continuous) is programmable.
A FEBE error is generated by forcing the C
inserted one error at a time, or continuously. The FEBE error insertion rate (single or continuous) is programmable.
Each error type (framing, P-bit parity, C-bit parity, or FEBE) has a separate enable. Continuous error insertion
mode inserts errors at every opportunity. Single error insertion mode inserts an error at the next opportunity when
requested. The framing multi-error modes (SEF or OOMF) insert the indicated number of error(s) at the next
opportunities when requested; i.e., a single request will cause multiple errors to be inserted. The requests can be
initiated by a register bit(TSEI) or by the manual error insertion input (TMEI). The error insertion initiation type
(register or input) is programmable. The insertion of each particular error type is individually enabled. Once all error
insertion has been performed, the data stream is passed on to overhead insertion.
10.10.5.4 Transmit C-bit DS3 Overhead Insertion
Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X
X
TOHSOFn). The P-bits (P
the input bit and the internally generated bit). The DS3 overhead insertion is fully controlled by the transmit
overhead interface. If the transmit overhead data enable signal (TOHENn) is driven high, then the bit on the
transmit overhead signal (TOHn) is inserted into the output data stream. Insertion of bits using the TOHn signal
overwrites internal overhead insertion.
2
, P
1
, P
2
13
, M
11
31
51
41
is overwritten with the Far-End Alarm and Control (FEAC) data input from the transmit FEAC controller.
, C
, C
, C
X
, C
1
, F
12
32
52
and P
XY
1
42
XY
, C
, and C
, and C
, M
) error. An M-bit error is a single multiframe alignment bit (M
, and C
, and C
21
2
, or M
, C
2
) are both overwritten with the calculated payload parity from the previous DS3 frame. The
33
53
22
, C
XY
are all overwritten with the calculated payload parity from the previous DS3 frame.
are overwritten with the path maintenance data link input from the HDLC controller.
43
1
3
) error in two consecutive DS3 frames.
and P
can be sourced from the transmit overhead interface (TOHCLKn, TOHn, TOHENn, and
23
are all overwritten with the Far-End Block Error (FEBE) bit. The FEBE bit can be
, C
61
2
, C
) and C
62
, C
63
31
41
, C
, C
, C
71
32
42
, C
, and C
, and C
72
, and C
X1
33
43
, F
bits are received as an error mask (modulo 2 addition of
bits in a single multiframe to zero. FEBE error(s) can be
73
X2
, F
are all overwritten with a one.
X3
31
, and F
, C
32
1
, and C
and P
X4
). An OOMF error is a single multiframe
1
, M
2
) in a single DS3 frame. P-bit parity
33
2
, or M
bits in a single DS3 frame. C-bit
3
) error. An SEF error is an
1
,