MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1001
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.7.5.3.2
Table 24-24
(three clocks). The example uses a 4-bit output port.
Note that T0, and I0 are the least significant bits where:
Tx = TCODE number (fixed)
Ix = Number of sequential instructions (variable)
24.7.5.4
Trace messages sent out may not be in the sequence they actually occurred. The traces are monitored on
the internal buses and these traces are captured as they occur and are sent out in the order they were
captured and processed.
BTMs are in sequence and DTMs are in sequence, however, temporal order of DTMs interleaved with
BTMs may not be accurate with regard to logical flow of code.
Freescale Semiconductor
is an example of the minimum transmission of any message containing a variable length field
Non-Temporal Ordering of Transmitted Messages
Example of Direct Branch Message
During clock 3, the tool should ignore data on MDO signals.
Clock
Clock
0
1
2
3
4
5
6
7
8
1
2
3
A3
A7
T3
T3
T3
I1
I5
I1
3
X
0
0
3
0
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 24-23. Indirect Branch Message
Table 24-24. Direct Branch Message
A2
A6
T2
T2
T2
I0
I4
I0
MDO[3:0]
X
MDO[3:0]
2
0
0
2
0
T1
T5
A1
A5
T1
T1
T5
I3
I7
X
1
0
1
0
NOTE
T0
T4
A0
A4
T0
T0
T4
I2
I6
X
0
0
0
0
MSEO
MSEO
1
1
0
0
0
1
0
1
1
0
1
0
1
1
Idle (or end of last
Normal Transfer
Normal Transfer
Normal Transfer
Start Message
Start Message
Start Message
End Message
End Message
End Packet
End Packet
End Packet
message)
Idle
Idle
READI Module
24-33
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