MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1096

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

MPC562/MPC564 Compression Features
A.2.8.2
Also created for branch instructions on the MPC562/MPC564, a bypass of 10 bits indicates that the AA
bit should be inserted with a value of zero and that the 5-bit word offset should be extended to 10 bits. The
decompression process is performed as shown in
This bypass is coded by a value of “12” (0xC) in the TP2LEN field of the DCCR register.
A.2.8.3
This MPC562/MPC564 bypass type indicates that no bypass data exists in the compressed instruction. The
bypassed segment is16 zero bits.
This bypass is coded by a value of “11” (0xB) in the TP2LEN field of the DCCR register.
A.2.9
The four possible compression layouts of an instruction and their attributes are listed in this section. See
Section A.4, “Decompressor Class Configuration Registers
attributes and more programming details.
A.2.9.1
This MPC562/MPC564 instruction is not compressed at all.
This class does not have a configuration register. Its prefix is hard-wired to ‘0000’ and no other attributes
are needed.
A-8
10-bit Compressed Bypass Field
Decompressed
Right Segment
MSB
0 0 0 0
Instruction Class Structures and Programming
Branch Right Segment Compression #2
Right Segment Zero Length Compression Bypass
Global Bypass
16
Figure A-5. Branch Right Segment Compression #2
32-bit segment – to be bypassed
w
Figure A-6. Global Bypass Instruction Layout
o r
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed Instruction
d
Compressed Instruction
o
f
32-bit bypass data
f
0
Figure
21
s
22
1
e
A-5.
t
(DCCR0-15),” for the instruction class
25
4 5
26
IP
8
29 30
Freescale Semiconductor
0
9
LK
31