MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 974

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
Vendor-defined messages outlined in
24.5
24-6
Auxiliary Port
Branch Trace Messaging
(BTM)
BDM
Compressed Code
Mode
Calibration Constants
Calibration Variables
Data Read Message
(DRM)
Data Write Message
(DWM)
Data Trace Messaging
(DTM)
Download
Field
FPM
IEEE-ISTO 5001
Halt
Instruction Fetch
Instruction Issue
60 (0x3C)
61 (0x3D)
Number
TCODE
Terms and Definitions
Term
Program Trace — Direct Branch Synchronization Message With Compressed Code. Available in
MPC562/MPC564 only.
Program Trace — Indirect Branch Synchronization Message With Compressed Code. Available in
MPC562/MPC564 only.
Refers to IEEE-ISTO 5001 auxiliary port.
External visibility of addresses for taken branches and exceptions, and the number of
sequential instructions executed between each taken branch.
Background Debug Mode.
Current instruction stream is fetching compressed code. Available in MPC562/MPC564 only.
Performance related constants which must be tuned for automotive powertrain and disk drive
applications.
Intermediate calculations which must be visible during the calibration or tuning process to
enable accurate tuning of calibration constants.
External visibility of data reads to internal memory-mapped resources.
External visibility of data writes to internal memory-mapped resources.
External visibility of how data flows through the embedded system. May include DRM and/or
DWM.
Tool sends information to the device
Number of bits representing single piece of information
Full Port Mode. This is the default full port mode for READI.
IEEE-ISTO 5001, formerly known as Global Embedded Processor Debug Interface
Standard. Worldwide web documentation at http://www.nexus5001.org/.
RCPU is in freeze state (typically in debug mode)
The process of reading the instruction data received from the instruction memory.
The process of driving valid instruction bits inside the processor. The instruction is decoded
by each execution unit, and the appropriate execution unit prepares to execute the instruction
during the next clock cycle.
Table 24-2. Vendor-Defined Messages (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 24-3. Terms and Definitions
Table 24-2
are also supported by READI.
Message Name
Description
Freescale Semiconductor