MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 783
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
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For example, with 0x00FF in the counter and 0x0002 in MPWMPULR2, the period is 255 PWM clock
count and the pulse width is 2 PWM clock counts.
For a given system clock frequency, with a given counter divide ratio and clock selection divide ratio, the
output pulse width is given by the following equation:
where V
In such conditions, the minimum output pulse width that can be obtained is given by:
and the maximum pulse width by:
17.10.3.5 Duty Cycles (0% and 100%)
The 0% and 100% duty cycles are special cases to give flexibility to the software to create a full range of
outputs. The “always set” and “always clear” conditions of the output flip-flop are established by the value
in register MPWMPULR2. These boundary conditions are generated by software, just like another pulse.
When the PWM output is being used to generate an analog level, the 0% and 100% represent the full scale
values.
The 0% output is created with a 0x0000 in register MPWMPULR2, which prevents the output flip-flop
from ever being set.
The 100% output is created when the content of register MPWMPULR2 is equal to or greater than the
content of register MPWMPERR. Thus, the width register match occurs on counter reload. The state
sequencer provides the timing to ensure that the first appearance of a 100% value in register
MPWMPULR2 causes a glitchless always-set condition of the output flip-flop when TRSP = ‘0’.
Freescale Semiconductor
MPWMB2
Even if the output is forced to 100%, the 16-bit up counter continues its
counting and that output changes to or from the 100% value are done
synchronously to the selected period.
When a PWM output period is selected to be 65536 PWM clocks by loading
0x0000 in the period register, it is not possible to have an 100% duty cycle
output signal. In this case, the maximum duty cycle available is of
65535/65536.
is the value in the register B2
Maximum_Pulse_Width
Pulse_Width
Minimum_Pulse_Width
MPC561/MPC563 Reference Manual, Rev. 1.2
=
=
N MCPSM N MPWMSM
---------------------------------------------------------------------------------------------------------------------------------------- -
N MCPSM N MPWMSM
-------------------------------------------------------------------------------------------------------- -
NOTE
NOTE
=
²
²
N MCPSM N MPWMSM
------------------------------------------------------------------ -
f SYS
f SYS
f SYS
²
²
²
(
V MPWMB2
2
Bit_of_Resolution
Modular Input/Output Subsystem (MIOS14)
–
1
)
17-51
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