MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 125

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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Table 2-11
of PDMCR2[PCS6EN], PDMCR2[PCS7EN], SHORT_REG [SH_ET1] and SHORT_REG [SH_ET2].
Also shown in this table is the internal connection of the ETRIG signals when the enhanced chip select
function is used.
Freescale Semiconductor
1. If PCS4/5EN = 1 then A/B_T2CLK into the module is pulled up internally (enabling Div/8 clock, in gate mode).
2. If only PCS4EN=1, then A_T2CLK can be driven into B_T2CLK if PPM_SHORT[SH_T2CLK] is set.
3. If only PCS5EN=1 then A_T2CLK will be pulled up, if PPM_SHORT[SH_T2CLK] is set, then, B_T2CLK will be high
All of this is regardless of the Pull up/down state.
Note: The PPM shorting function has higher priority logic. If shorting is selected, then A_T2CLK → B_T2CLK. If A_T2CLK
[PCS5EN]
PDMCR2
regardless of pin state.
0
1
1
1
1
is selected as PCS then both A_T2CLK and B_T2CLK will be high regardless of B_T2CLK/PCS4 Pad state.
details the functionality of the ETRIG1/PCS6 and ETRIG2/PCS7 pads dependent on the values
[PCS4EN]
PDMCR2
1
0
0
1
1
SHORT_REG
[SH_T2CLK]
Table 2-10. Enhanced PCS 4 & 5 Pad Function
1
0
1
0
1
MPC561/MPC563 Reference Manual, Rev. 1.2
A_T2CLK/PCS5
PAD Function
A_T2CLK
PCS5
PCS5
PCS5
PCS5
B_T2CLK/PCS4
PAD Function
B_T2CLK
B_T2CLK
PCS4
PCS4
PCS4
A_T2CLK internal
driven HI internally
driven HI internally
driven HI internally
driven HI internally
A_T2CLK Signal
A_T2CLK Signal
A_T2CLK Signal
A_T2CLK Signal
A_T2CLK/PCS5
Connection
TPU_A
Pad
B_T2CLK internal
driven HI internally
driven HI internally
driven HI internally
B_T2CLK Signal
B_T2CLK Signal
B_T2CLK Signal
A_T2CLK/PCS5
B_T2CLK/PCS4
by connection to
by connection to
Connection
Signal Descriptions
A_T2CLK
A_T2CLK
TPU_B
Pad
Pad
2-27

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