MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 522
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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QADC64E Legacy Mode Operation
The remaining situations, S6 through S11, show the impact of a queue 1 trigger event occurring during
queue 2 execution. Queue 1 is higher in priority the conversion taking place in queue 2 is aborted, so that
there is not a variable latency time in responding to queue 1 trigger events.
In situation S6
before the conversion is complete, so that queue 1 execution can begin. Queue 2 is considered suspended.
After queue 1 is finished, queue 2 starts over with the first CCW, when the RES (resume) control bit is set
to 0. Situation S7
suspension works the same way.
13-58
Q1
Q2
QS
Q1
Q2
QS
(Figure
(Figure
IDLE
IDLE
0000
0000
IDLE
IDLE
13-32), the conversion initiated by the second CCW in queue 2 is aborted just
13-33) shows that when pause operation is not in use with queue 2, queue 2
Q1:
Q1:
Q2:
T1
T1
1000
MPC561/MPC563 Reference Manual, Rev. 1.2
C1
C1
ACTIVE
Figure 13-31. CCW Priority Situation 5
Figure 13-32. CCW Priority Situation 6
ACTIVE
1000
T2
TOR2
TRIG
1011
C2
C2
T2
PF1
PF1
0100
Q2:
C1
ACTIVE
0110
T2
PAUSE
PAUSE
C2
C1
ACTIVE
0110
PF2
0101 1001 1011
C2
PAUSE
T1
T1
SUSPEND
C3
C3
ACTIVE
ACTIVE
ACTIVE
ACTIVE
1010
T2
TRIG
TOR2
C4
T2
C4
CF1
CF1
C1
C3
ACTIVE
0010
C4
C2
RESUME=0
ACTIVE
0010
CF2
C3
IDLE
IDLE
C4
Freescale Semiconductor
IDLE
0000
CF2
IDLE
0000
QADC S5
QADC S6
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