MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 896

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CDR3 Flash (UC3F) EEPROM
CENSOR[0:1] transitions are listed as follows:
21.3.12 Background Debug Mode or Freeze Operation
While in background debug mode, the UC3F should respond normally to accesses except that LOCK is
writable. See the LOCK bit in
21-34
1. Cleared censorship to no censorship, T1
2. No censorship to information censorship, T2
3. Information censorship, no censorship or unknown to cleared censorship, T3
4. Cleared censorship to information censorship, T4
Set CENSOR[0] or CENSOR[1].
Set CENSOR[0] and CENSOR[1].
Clear CENSOR[0:1]. This is done only while the entire UC3F array is erased.
Set both CENSOR[0] and CENSOR[1].
Table
MPC561/MPC563 Reference Manual, Rev. 1.2
21-3.
Freescale Semiconductor