MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 183

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

subsequent instruction. Blockage refers to the interval from the time an instruction begins execution until
its execution unit is available for a subsequent instruction.
3.13
3.13.1
The RCPU is a 32-bit implementation of the PowerPC ISA architecture. Any reference in the PowerPC
ISA architecture books (UISA, VEA, OEA) regarding 64-bit implementations are not supported by the
core. All registers except the floating-point registers are 32 bits wide.
3.13.2
Reserved fields in instructions are described under the specific instruction definition sections. Unless
otherwise noted, reserved fields should be written with a zero when written and return a zero when read.
Thus, this type of invalid form instructions yield results of the defined instructions with the appropriate
field zero.
In most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any
control register implemented by the MPC561/MPC563. Exception to this rule are bits [16:23] of the
fixed-point exception cause register (XER) and the reserved bits of the machine state register (MSR),
which are set by the source value on write and return the value last set for it on read.
Freescale Semiconductor
User Instruction Set Architecture (UISA)
Computation Modes
Reserved Fields
When the blockage equals the latency, it is not possible to issue another
instruction to the same unit in the same cycle in which the first instruction
is being written back.
1
Refer to Section 7, “Instruction Timing,” in the RCPU Reference Manual
(RCPURM/AD) for details.
Floating-point multiply
Floating-point divide
Instruction Type
Integer load/store
Integer multiply
add or subtract
Floating-point
Floating-point
Integer divide
multiply-add
Table 3-20. Instruction Latency and Blockage
MPC561/MPC563 Reference Manual, Rev. 1.2
Precision
Double
Double
Double
Double
Single
Single
Single
Single
—
—
—
NOTE
See note
Latency
2 to 11
17
10
7
6
4
4
5
4
2
1
1
Blockage
See note
2 to 11
1 or 2
17
10
7
6
4
4
5
4
1
1
1
Central Processing Unit
3-39