MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 498

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
corresponding locations in the result word table as scratch pad RAM, remembering that only 10 bits are
implemented. The result alignment is only implemented for software read operations. Since write
operations are not the normal use for the result registers, only one write data format is supported, which is
right justified data.
13.4
This section describes the QADC64E analog subsystem, which includes the front-end analog multiplexer
and analog-to-digital converter.
13.4.1
The analog subsystem consists of the path from the input signals to the A/D converter block. Signals from
the queue control logic are fed to the multiplexer and state machine. The end of convert (EOC) signal and
the successive-approximation register (SAR) are the result of the conversion.
diagram of the QADC64E analog subsystem.
13-34
Analog Subsystem
Analog-to-Digital Converter Operation
Some write operations, like bit manipulation, may not operate as expected
because the hardware cannot access a true 16-bit value.
AN44
AN59
V
V
.
. .
RH
RL
Figure 13-20. QADC64E Analog Subsystem Block Diagram
CCW Buffer
Data Bus
CHAN
Decoder
6
10
MPC561/MPC563 Reference Manual, Rev. 1.2
Sample
REF
IST
+
-
Result
Buffer
AMP
State Mach, SAR and SAR Buffer
RDAC
(7 BIT)
NOTE
7
Standard Converter Interface
CONV.
Final
Buffer
WCCW EOS/EOC
STOP
Sample
CAP Array
Equals CDAC
CRH
CRL
CDAC
(4 BIT)
4 (one is offset)
CLK
BIAS
Figure 13-20
-
+
COMP.
Zero
Freescale Semiconductor
2
shows a block