MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 172
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Central Processing Unit
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The
PowerPC ISA architecture uses instructions that are four bytes long and word-aligned. It provides for byte,
half-word, and word operand loads and stores between memory and a set of 32 GPRs.
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with distinct instructions.
PowerPC ISA-compliant processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an instruction or by an
asynchronous event. Either kind of exception may cause one of several components of the system software
to be invoked.
3.10.1
Table 3-17
description of the instruction set.
3-28
add (add. addo addo.)
addc (addc. addco addco.)
adde (adde. addeo addeo.)
addi
addic
addic.
addis
addme (addme. addmeo addmeo.)
addze (addze. addzeo addzeo.)
and (and.)
andc (andc.)
andi.
andis.
b (ba bl bla)
— Synchronize
— Instruction synchronize
provides a summary of RCPU instructions. Refer to the RCPU Reference Manual for a detailed
Instruction Set Summary
This grouping of the instructions does not indicate which execution unit
executes a particular instruction or group of instructions.
Mnemonic
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-17. Instruction Set Summary
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,SIMM
rD,rA,SIMM
rD,rA,SIMM
rD,rA,SIMM
rD,rA
rD,rA
rA,rS,rB
rA,rS,rB
rA,rS,UIMM
rA,rS,UIMM
target_addr
Operand Syntax
NOTE
Add
Add Carrying
Add Extended
Add Immediate
Add Immediate Carrying
Add Immediate Carrying and Record
Add Immediate Shifted
Add to Minus One Extended
Add to Zero Extended
AND
AND with Complement
AND Immediate
AND Immediate Shifted
Branch
Name
Freescale Semiconductor
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