MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 256

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6.1.4.5
The interrupt overhead consists of two main parts:
The interrupt overhead can increase latency, and decrease the overall system performance. The overhead
of register saving time can be reduced by improving the operating system. The number of registers that
should be saved can be reduced if each interrupt event has its own interrupt vector. This solution solves
the interrupt source recognition overhead.
Only registers required for the recognition routine are considered to be saved in the calculations below.
Recognition of module internal events/channels is out of the scope of the calculations. See also the typical
interrupt handler flowchart in
6-16
•
•
Operation
Storage of general and special purpose registers
Recognition of the interrupt source
Details
Notes:
Total:
Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode
Compiler and bus collision overhead are not included in the calculations.
If there is a need to enable
At Least 70-80 Clocks
Interrupt propagation from
request module to RCPU —
Store of some GPR and
SPR—10 clocks
Read SIPEND—4 clocks
Read SIMASK—4 clocks
SIPEND data processing —
20 clocks
(find first set, access to LUT in
the Flash, branches)
Read UIPEND—4 clocks
UIPEND data processing—20
clocks
(find first set, access to LUT in
the Flash, branches)
nesting of interrupts during
source recognition procedure,
at least 30 clocks should be
added to the interrupt latency
estimation
Architecture Without Using
8 clocks
Table 6-5. Interrupt Latency Estimation for Three Typical Cases
MPC561/MPC563
SIVEC
Figure
MPC561/MPC563 Reference Manual, Rev. 1.2
6-6.
Table 6-5
Interrupt propagation from
request module to RCPU —
Store of some GPR and SPR
—10 clocks
Read SIVEC—4 clocks
Branch to routine—10 clocks
Read UIPEND—4 clocks
UIPEND data processing —
(find first set, access to LUT in
the Flash, branches)
To use this feature in compressed
mode some undetermined
latency is added to make a
branch to compressed address of
the routine. This latency is
dependant on how the user code
is implemented.
At Least 50-60 Clocks
MPC561/MPC563 Architecture
8 clocks
20 clocks
NOTE
below illustrates the improvements.
Using SIVEC
Interrupt propagation from
request module to RCPU —
Store of some GPR and
SPR—10 clocks
Only one branch is executed to
reach the interrupt handler
routine of the device requesting
interrupt servicing—2 clocks
—
20 Clocks
6 clocks
Enhanced Interrupt
Controller Features
Architecture Using
MPC561/MPC563
Freescale Semiconductor