MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 32

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

24.7.7.3
24.7.7.4
24.7.7.5
24.8
24.8.1
24.8.1.1
24.8.2
24.8.2.1
24.8.2.2
24.8.2.3
24.8.2.4
24.8.2.4.1
24.8.2.4.2
24.8.2.4.3
24.8.2.4.4
24.8.2.4.5
24.8.2.5
24.8.2.6
24.8.3
24.8.4
24.8.4.1
24.8.4.2
24.8.4.3
24.8.4.4
24.8.5
24.8.6
24.8.7
24.9
24.9.1
24.9.2
24.9.2.1
24.9.2.2
24.9.2.3
24.9.2.4
24.9.2.5
24.9.2.6
24.9.3
24.9.4
24.9.5
24.9.6
24.9.7
Freescale Semiconductor
Paragraph
Number
Program Trace ............................................................................................................ 24-38
Data Trace .................................................................................................................. 24-52
Branch Trace Messaging ........................................................................................ 24-38
BTM Message Formats ........................................................................................... 24-38
Queue Overflow Program Trace Error Message .................................................... 24-47
Branch Trace Message Operation ........................................................................... 24-47
Branch Trace Message Queueing ........................................................................... 24-48
BTM Timing Diagrams .......................................................................................... 24-49
Program Trace Guidelines ...................................................................................... 24-51
Data Trace for the Load/Store Bus (L-Bus) ............................................................ 24-52
Data Trace Message Formats .................................................................................. 24-52
Queue Overflow Data Trace Error Message ........................................................... 24-54
Data Trace Operation .............................................................................................. 24-54
Data Trace Windowing ........................................................................................... 24-56
Special L-Bus Cases ............................................................................................... 24-56
Data Trace Queuing ................................................................................................ 24-56
Secure Mode ....................................................................................................... 24-37
Disabled Mode .................................................................................................... 24-37
Guidelines for Transmitting Input Messages ...................................................... 24-37
RCPU Instructions that Cause BTM Messages .................................................. 24-38
Direct Branch Messages ..................................................................................... 24-38
Indirect Branch Messages ................................................................................... 24-39
Correction Messages ........................................................................................... 24-40
Synchronization Messages .................................................................................. 24-42
Error Messages ................................................................................................... 24-46
Relative Addressing ............................................................................................ 24-46
BTM Capture and Encoding Algorithm ............................................................. 24-47
Instruction Fetch Snooping ................................................................................. 24-48
Instruction Execution Tracking .......................................................................... 24-48
Instruction Flush Cases ....................................................................................... 24-48
Data Write Message ............................................................................................ 24-52
Data Read Message ............................................................................................. 24-53
Data Trace Synchronization Messages ............................................................... 24-53
Data Write Synchronization Message ................................................................ 24-54
Data Read Synchronization Messaging .............................................................. 24-54
Relative Addressing ............................................................................................ 24-54
Direct Branch Synchronization Message ....................................................... 24-44
Indirect Branch Synchronization Message ..................................................... 24-44
Direct Branch Synchronization Message With Compressed Code ................ 24-44
Indirect Branch Synchronization Message with Compressed Code ............... 24-45
Resource Full Message ................................................................................... 24-45
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
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Number
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