MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 442

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

L-Bus to U-Bus Interface (L2U)
When the access by the RCPU is not permitted, the L2U module asserts a data memory storage exception
to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded (G bit of region attribute
register is set), the L2U asks the RCPU to retry the L-bus cycle until either the access is not speculative,
or is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protection violation (no
access), the L2U retries the access. The L2U handles this event as a data storage violation only when the
access becomes non-speculative.
Note that access protection is active only when the MPC500’s MSR[DR] = 1. When MSR[DR] = 0, DMPU
exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative
accesses are allowed. In this case, if the L-bus master [RCPU] initiates a non-CALRAM cycle (access
through the L2U) that is marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either
the access is not speculative, or it is canceled by the RCPU Core.
11.5.2
Table 11-1
special purpose registers that are accessed via the MPC500 mtspr/mfspr instructions. The registers are also
accessed by an external master when EMCR[CONT] = 0. See
for register diagrams and bit descriptions.
11-6
.
shows registers that are used to control the DMPU of the L2U module. All the registers are
Associated Registers
The programmer must not overlap the CALRAM memory space with any
enabled region. Overlapping an enabled region with CALRAM memory
space disables the L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all
accesses to addresses within the L-bus space. If an enabled region overlaps
with MPC500 register addresses, the DMPU ignores any access marked as
an MPC500 access.
L2U_RBA0
L2U_RBA1
L2U_RBA2
L2U_RBA3
L2U_GRA
L2U_RA0
L2U_RA1
L2U_RA2
L2U_RA3
Name
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 11-1. DMPU Registers
Region Base Address Register 0
Region Base Address Register 1
Region Base Address Register 2
Region Base Address Register 3
NOTE
Region Attribute Register 0
Region Attribute Register 1
Region Attribute Register 2
Region Attribute Register 3
Global Region Attribute
Description
Section 11.8, “L2U Programming
Freescale Semiconductor
Model,”