MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1210

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

TPU3 ROM Functions
active, these performance figures will be degraded; however, the scheduler assures that the worst-case
latency in any TPU3 application can be closely approximated. TPU3 reference manual guidelines and
information given in the SIOP-state timing table should be used to perform an analysis on any proposed
TPU3 application that appears to approach the TPU’s performance limits.
D.20.3.1
XFER_SIZE is normally programmed to be in the 1- to 16-bit range to match the size of SIOP_DATA, and
has thus been shown as a 5-bit value in the host interface diagram. However, the TPU3 actually uses all 16
bits of the XFER_SIZE parameter when loading BIT_COUNT. In some unusual circumstances this can be
used to an advantage. If an input device is producing a data stream of greater than 16 bits then manipulation
of XFER_SIZE will allow selective capturing of the data. In clock-only mode, the extended XFER_SIZE
can be used to generate up to 0xFFFF clocks.
D.20.3.2
As stated above, the TPU3 does not “justify” the data position in SIOP_DATA. Therefore, in the case of a
byte transfer, the data output will be sourced from one byte and the data input will shift into the other byte.
This is true for all data sizes except 16 bits, in which case the full SIOP_DATA register is used for both
data output and input.
D.20.3.3
In the example given in
synchronous with the relevant clock edge and it is assumed that the data input is latched exactly on the
opposite clock edge. This is the simplest way to show the examples, but is not strictly true. Since the TPU3
is a multi-tasking system, and the data channels are manipulated directly by microcode software while
servicing the clock edge, there is a finite delay between the relevant clock edge and the data-out being valid
or the data-in being latched. This delay is equivalent to the latency in servicing the clock channel due to
other TPU3 activity and is shown as ‘Td’ in the timing diagram. Td is the delay between the clock edge
and the next output data being valid and also the delay between the opposite clock edge and the input data
being read. For the vast majority of applications, the delay Td will not present a problem and can be
ignored. Only for a system which heavily loads the TPU3 should the worst case latency be calculated for
D-58
1
Execution times do not include the time slot transition time (TST = 10 or 14 RCPU clocks).
State Number and Name
XFER_SIZE Greater Than 16
Data Positioning
Data Timing
S2 DATA_OUT
S1 SIOP_INIT
S3 DATA_IN
HSQ = X0
HSQ = X0
HSQ = 0X
X1
X1
1X
Figure
D-33, the data output transitions are shown as being completely
MPC561/MPC563 Reference Manual, Rev. 1.2
Table D-4. SIOP State Timing
Max. RCPU Clock Cycles
28
38
14
24
14
28
1
Number of RAM Accesses by TPU3
Freescale Semiconductor
7
7
4
4
4
6